Browse Prior Art Database

Single Cycle Store in a Single Ported Tag Implementation

IP.com Disclosure Number: IPCOM000117879D
Original Publication Date: 1996-Jul-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Eisen, L: AUTHOR [+4]

Abstract

Disclosed is a scheme where the access to the cache for a store request is split up into the tag access and the cache array access which enables pipelining of back to back stores. The mechanism allows to execute stores in fully pipelined fashion with a clock latency of one store per cycle.

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Single Cycle Store in a Single Ported Tag Implementation

Disclosed is a scheme where the access to the cache for a store
request is split up into the tag access and the cache array access
which enables pipelining of back to back stores.  The mechanism
allows to execute stores in fully pipelined fashion with a clock
latency of one store per cycle.

The LSU unit consists of a 3-staged address pipeline for stores:

1.  The effective address state (EA state) wherein the effective
    address of the store instruction is computed.

2.  The faultable store state (FSQ state) wherein the address,
    hit/miss, way etc. information generated from the tag lookup is
    stored in finished store Q(FSQ).

3.  The committed store state (CSQ state) wherein the index of the
    store instruction along with the hit/miss, way information from
    the FSQ is store in committed store Q(CSQ).

          Fig. 1   Address Path Design For Single Cycle Store

When the store is in EA state, the upper 21 (Fig. 1) bits of the
address is sent to MMU for the address translation.  If the
translation has been enabled, the translated address from the MMU is
compared with the tags indexed by the lower bits of the EA.  If the
tags match, then hit is signalled from the tag array which is latched
in FSQ.  In the same cycle (FSQ state), the MMU indicates whether any
exception has occurred (due to protection violation or page faults
etc.).  In the case of an exception, the store access...