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Pin Function Multiplexing Circuit

IP.com Disclosure Number: IPCOM000117904D
Original Publication Date: 1996-Jul-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Gowda, S: AUTHOR [+4]

Abstract

A circuit to allow the power shutdown, SD, and transmit signal, TX, pins of a transceiver circuit to be used to also select another mode of the circuit; namely to switch between two band-width states. The circuit also insures that during power on the mode is in the off state (low bandwidth mode) and the transmit circuit is disabled during the multiplexing operation. The mode multiplexing is accomplished by using the SD pin to clock the state of the TX pin using a D type latch, I0, and inverter, I5, (Fig. 1). The mode is forced low during powerup using the circuit consisting of I3, I10, I15, I16 and I1. At power on the signals, pon, and SD are low forcing the "sel" input to the NAND gate, I3, to be low forcing MODE to be low throughout the power up sequence.

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Pin Function Multiplexing Circuit

      A circuit to allow the power shutdown, SD, and transmit signal,
TX, pins of a transceiver circuit to be used to also select another
mode of the circuit; namely to switch between two band-width states.
The circuit also insures that during power on the mode is in the off
state (low bandwidth mode) and the transmit circuit is disabled
during the multiplexing operation.  The mode multiplexing is
accomplished by using the SD pin to clock the state of the TX pin
using a D type latch, I0, and inverter, I5, (Fig. 1).  The mode is
forced low during powerup using the circuit consisting of I3, I10,
I15, I16 and I1.  At power on the signals, pon, and SD are low
forcing the "sel" input to the NAND gate, I3, to be low forcing MODE
to be low throughout the power up sequence.  The first time SD goes
high, after pon becomes high, the sel output goes high allowing the
flipflop to control the mode state.

      The circuit in Fig. 2 insures that the tx_enable signal is
disabled during the multiplexing operation.  The NOR gate, I1, two
inverters, I3 and I4 and the NAND gate, I9, form a latch that
disables the LED enable signal during the multiplexing operation.
When tx and pon are high (when the led signal must be disabled and
after the power on sequence) the circuit is latched by SD going high.
It stays latched until SD goes low again thus turning off tx_enable.