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Browse Prior Art Database

Method for Adding Request/Grant Pairs to a Fixed Peripheral Component Interconnect Arbiter

IP.com Disclosure Number: IPCOM000117909D
Original Publication Date: 1996-Jul-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 160K

Publishing Venue

IBM

Related People

Begun, RM: AUTHOR [+2]

Abstract

This invention provides a method and implementation of adding more devices to a Peripheral Component Interconnect (PCI) bus than the existing system arbiter can handle. It does so by sharing multiple request/grant pairs on one of the arbiter's request/grant lines. The invention provides methods and implementations of two kinds of fairness strategies to ensure that the devices that are sharing the one request/grant pair get fair access to the bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Method for Adding Request/Grant Pairs to a Fixed Peripheral Component
Interconnect Arbiter

      This invention provides a method and implementation of adding
more devices to a Peripheral Component Interconnect (PCI) bus than
the existing system arbiter can handle.  It does so by sharing
multiple request/grant pairs on one of the arbiter's request/grant
lines.  The invention provides methods and implementations of two
kinds of fairness strategies to ensure that the devices that are
sharing the one request/grant pair get fair access to the bus.

      There will often be a need to attach more PCI bus agents to the
PCI bus than a given central arbitration resource can connect.  This
invention presents logic that can expand a single PCI bus arbitration
resource connection.

      Current PC Computers and Workstations are being designed with
an internal bus structure known as the PCI bus.  Personal computer
systems employing the PCI bus must provide an arbitration mechanism
for multiple PCI bus master devices, in order to allocate access to
the PCI bus.  This arbitration mechanism is a central resource that
communicates with bus agents via request/grant pairs.  Any such
central resource that is implemented in VLSI logic must, due to
practical constraints, limit the number of request/grant pairs that
it may service.  However, system applications are always expanding,
with additional devices like multi-media options, fax/modems, and
communication attachments becoming rapidly available.

      The Peripheral Component Interconnect (PCI) bus is a popular
industry standard bus designed to be a core bus in personal computer
systems.  This bus is well documented in the "Peripheral Component
Interconnect (PCI) Revision 2.1 Specification."

      The multiple bus devices that the PCI bus supports are
connected via a common PCI bus.  To gain access to this bus, each
device is required to use a request/grant protocol.  This protocol
uses the REQ_/GNT_ signals as documented in the PCI specification.

The multiple REQ_/GNT_ pairs are then connected to a central
arbitration resource.  This Central Arbitration Resource (CAR)
accepts all REQ_/GNT_ pairs and determines which PCI device will be
allowed to access the PCI bus at the next available opportunity.
This is shown in Fig. 1.

      As previously discussed, any CAR can only provide a fixed
number of request grant pairs.  Note that some prior art arbitration
schemes, such as that provided by the Micro Channel, use binary
encoding schemes whereby for example 16 agents may be attached via 4
arbitration lines.  The PCI approach is more straightforward, but has
as a disadvantage the requirement of additional I/O signals.  The
same 16 agents on the PCI bus would require 32 I/O lines (16
REQ_/GNT_ pairs).

      This invention then, proposes a means whereby a single
request/grant pair can be expanded into multiple request/grant pairs
with relatively simple external logic.

...