Browse Prior Art Database

Cascade Digital Phase Aligner

IP.com Disclosure Number: IPCOM000117919D
Original Publication Date: 1996-Jul-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 98K

Publishing Venue

IBM

Related People

Casal, H: AUTHOR [+4]

Abstract

Disclosed is a method of minimizing global system clock skew by utilizing multiple levels of the Digital Phase Aligner (DPA). This scheme makes the clock arrival times the same even though there may be unequal electrical path lengths from one FRU to another.

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This is the abbreviated version, containing approximately 52% of the total text.

Cascade Digital Phase Aligner

      Disclosed is a method of minimizing global system clock skew by
utilizing multiple levels of the Digital Phase Aligner (DPA).  This
scheme makes the clock arrival times the same even though there may
be unequal electrical path lengths from one FRU to another.

      An advanced high performance processor system that consists of
multiple chips requires a sophisticated clocking system to provide
the clock controls to each element.  The time accuracy and delay skew
of the clock subsystem is major detractor to overall system
performance as the cycle time of the system is reduced.  The
objective is to minimize the time difference between the clock
arrival between any two or more elements in the system.

      The basic element used is the Digital Phase Aligner (DPA) as
shown in Figs. 1A and 1B.  Also, the clock distribution diagram is
illustrated in Fig. 2.

      The key characteristic of the DPA is that it adjusts the delay
as seen by the clock from FRU #1 to FRU #2 using variable delay
elements such that the delay from FRU #1 to FRU #2 is equivalent to
the delay from FRU #1 to FRU #n.  If this is done perfectly then the
clocks should arrive at FRU #2 at exactly the same time it arrives at
FRU #n.  In this ideal environment the clock skew is totally
eliminated (discounting noise and other disturbances.)

      The DPA (Fig. 1A) for the inter-FRU skew adjustment uses a
feedback path that also has an adjustable delay elements and adjusts
the return path delay to equal the outgoing or transmitted path
delay.  This is done by the phase detector shown in the DPA that
detects the condition that the arrival transition of the two clock
times are the same, i.e., the transmitted and the received clock is
exactly in phase.

      Note also a important calibration capability in the DPA using
the incom...