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Browse Prior Art Database

Sharing Data Bus and Channel Control Register

IP.com Disclosure Number: IPCOM000117929D
Original Publication Date: 1996-Jul-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Matsubara, N: AUTHOR [+3]

Abstract

Disclosed is a high speed interface method between a read/write channel and a Hard Disk Controller (HDC) and a Micro Processor Unit (MPU).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Sharing Data Bus and Channel Control Register

      Disclosed is a high speed interface method between a read/write
channel and a Hard Disk Controller (HDC) and a Micro Processor Unit
(MPU).

This interface comprises the following features:
  1.  Customer data bus and channel control register are shared inthe
       same pins.
  2.  Channel control register are read or written in parallel, in
the
       sequence of address and data.
  3.  Channel control register is modified asynchronously by the
       channel read reference clock.

The Figure shows an example algorithm of this interface.

      In accordance with this method, the channel register transfer
time is minimized to three channel register clocks, for example.
This high speed channel register transfer method is useful especially
in Partial Response Maximum Likelihood (PRML) channel application
which uses a lot of register.