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Swap Master Processor during OpenFirmware Execution in an Symmetrical Multi-Processor RS/6000 Machine

IP.com Disclosure Number: IPCOM000117975D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Lee, VH: AUTHOR

Abstract

Disclosed is a procedure for changing the Open-Firmware master processor in a Symmetrical Multi-Processor (SMP) machine. This method can be performed whenever it is desired. And the entire procedure is transparent and not disrupting the current operation of the Open Firmware of the system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Swap Master Processor during OpenFirmware Execution in an Symmetrical
Multi-Processor RS/6000 Machine

      Disclosed is a procedure for changing the Open-Firmware master
processor in a Symmetrical Multi-Processor (SMP) machine.  This
method can be performed whenever it is desired.  And the entire
procedure is transparent and not disrupting the current operation of
the Open Firmware  of the system.

      In the SMP machine with Open Firmware (OF) support, the master
processor is the processor which is executing the Open Firmware of
the system.  Other processors, if present, are put into a stopped
state which  shall not interfere with the operation of the master.

      In order to transfer the execution of the Open Firmware to a
stopped processor, the current master processor will need to execute
an Open Firmware method which will perform the following steps:
  1.  From the Open Firmware device tree, the current master
       processor obtains its device nodes's package handle
       (phandle) and the phandle of the device node of the
       soon-to-be master processor.
  2.  With these phandles, the current master processor will swap
       all processor related properties between the two involved
       processor nodes.  "Reg" property, "cpu-version" property,
       etc. are just some examples.  This step converts the device
       node for the current master processor into the device node
       for the soon-to-be master processor, and vice verse.
  3.  With the changes in step 2, the current master processor
       will now need to correct the device tree so that the
       processor's child nodes, i.e., L2 cache nodes, will have
       their parent nodes swapped.  Then the "L2-cache" properties
       of the processor nodes need to be swapped as well.
  4.  The current master processor saves the current system reset
       interrupt handler and installs a new system reset interrupt
       handler.  For example, the PowerPC* processor has the system
       reset interrupt vector at system real address 0x100, and the
       new handler will look like belows.
  bl     $+8         #
  .long  0xHHHHHHHH  # IIIIIIII = real address of register image
  .long  0xIIIIIIII  # HHHHHHHH = real address that the stopped
  mflr   r3          # processor will begin execution within OF.
  lwz    r0,0(r3)    # R0 = HHHHHHHH
  mtlr   r0          # Set up HHHHHHHH as branch target
  lwz    r0,4(r3)    #
  mtctr  r0          # Save IIIIIIII in CTR temporarily
  addi   r0,r0,0     # R0 = 0
  stwx   r0,0(r3)    # 0 -> @(0x104)
  sync               #
  blr                # Branch to HHHHHHHH
  5.  The open firmware code at real address 0xHHHHHHHH are
       assembly language instructions likes these.
  lwz    r4,0(...