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Browse Prior Art Database

Transmission Line Scheme to Feed Several Line Receivers

IP.com Disclosure Number: IPCOM000117984D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Radius, R: AUTHOR

Abstract

Disclosed is a scheme of high frequency transmission lines, which minimizes the differences in access time from one driver to several devices.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Transmission Line Scheme to Feed Several Line Receivers

      Disclosed is a scheme of high frequency transmission lines,
which minimizes the differences in access time from one driver to
several devices.

      In high density high speed memory cards with several hundreds
of RAM modules to be accessed by a single driver chip, the control
lines of several RAMs have to be connected together.  With cycle
times in the  nanosecond region, all RAM inputs should be accessed
with very small timing differences.

      One solution is to split the feeding line into several lines
with symmetric input loads at their ends as shown in Fig. 1.

      If, for design flexibility reasons, the load consists of 9 or
10 RAM inputs, the concept of splitting the feeding line leads with
10 RAM input loads to a unbalanced situation which results in slope
reversals of the pulse edges and unprecise timing.

      The proposed net configuration (Fig. 2) balances the timing
differences between the input loads.  With properly chosen feeding
points, A, B and C driving 9 or 10 loads is possible with tolerable
timing differences between the loads.