Browse Prior Art Database

Dual 64-Bit Address Peripheral Component Interconnect

IP.com Disclosure Number: IPCOM000117985D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Neal, D: AUTHOR [+2]

Abstract

Currently, the Peripheral Component Interconnect (PCI) architecture includes a definition of 64-bit addressing capability independent of the bus width of the master/target (32-bit or 64-bit), but cannot presently provide addressing above 64-bits. This invention discloses means to provide for a dual 64-bit address cycle, which allows up to 128-bits of PCI addressing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Dual 64-Bit Address Peripheral Component Interconnect

      Currently, the Peripheral Component Interconnect (PCI)
architecture includes a definition of 64-bit addressing capability
independent of the bus width of the master/target (32-bit or 64-bit),
but cannot presently provide addressing above 64-bits.  This
invention discloses means to provide for a dual 64-bit address cycle,
which allows up to 128-bits of PCI addressing.

      Fig. 1 illustrates a basic Read operation using the dual 64-bit
address command.  This command would use of one of the presently
reserved PCI command codes to allow expansion of the addressing
capability of the  PCI bus to 128 bits, much the same way the
currently defined PCI Dual Address Cycle (DAC) command code allows
the expansion of the PCI addressing from 32-bits to 64-bits.

      Referring to Fig. 1, during the first cycle of the dual 64-bit
address cycle, the low order 64-bits (63::0) of the address are
placed on the address bus.  During the second cycle of the dual
64-bit address  cycle, the high order 64-bits (127::64) of the
address are placed on the address bus.  This then completes the
address phase of the dual 64-bit address cycle, which can provide up
to 128 bits of PCI bus addressing.  If less than 128 bits of
addressing is desired but greater  than 64-bits (for example,
96-bits), the higher order 32-bits of the second address cycle would
be all zero's.

      During the first address cycle, the Dual 64-bi...