Browse Prior Art Database

Generic Performance Monitor Interface Approach

IP.com Disclosure Number: IPCOM000117995D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 171K

Publishing Venue

IBM

Related People

Levine, FE: AUTHOR

Abstract

An application interface is provided which maps data from a generic processor independent format to a machine specific format.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 30% of the total text.

Generic Performance Monitor Interface Approach

      An application interface is provided which maps data from a
generic processor independent format to a machine specific format.

      The support for performance monitoring is now being added to
Microprocessors with each processor typically providing a different
set of functions and a different means to access the same functions.
Many processor implementations are not disclosed to the end user in
order to avoid the expected end user request for binary compatibility
in future versions of the same or similar processors.  Because the
performance monitoring support is not required to support the user
instruction set, the processor designers and instruction architects
do not see a need for a consistent user interface.  Also, the fact
that performance tuning tends to be machine specific promotes the
notion that consistency is not required.  On the other hand, in order
to provide for a set of tools that don't require change when a new
processor is supported, there needs to be some consistency in the way
the tools access the performance monitor.  Without a consistent
interface the tools will need to be changed and the software bill
including the testing to provide this support becomes prohibitive.

      The PowerPC* 6XX Performance Monitor is a software accessible
mechanism intended to provide detailed information concerning the
utilization of PowerPC instruction execution and storage control.
The monitor consists of an implementation dependent number (2-8)
32-bit counters (PMC1, PMC2, PMC3, ..., PMC8) to be used to count
Processor/Storage performance related events.

      The Monitor Mode Control Registers (MMCRn) establish the
function of the counters.  The counters and the MMCRn physically
reside on the 6XX chip and are addressable for read or write via
mfspr or mtspr  instructions.  Writing to these SPRs is only allowed
in privileged state.  Reading from these SPRs may also be allowed in
the problem state.  Reading these counters/registers does not change
their content.

      The Monitor Mode Control Registers (MMCRn) are partitioned
into bit fields that allow for selection of events (signals) to be
recorded (counted).  Selection of allowable combinations of events,
causes the counters to operate concurrently.  The MMCRn includes
controls, such as, counter enable controls, counter overflow
interrupt controls, counter event selections, and counter freeze
controls.

      The PowerPC 6XX chips which support Performance Monitoring
contains an implementation dependent number of events that can be
selected for counting.
  - When processors are under development, the decision as to
     the number of counters and the actual support provided in
     the processor is typically thought to be an implementation
     detail.  The performance monitor function is not required
     to meet the Operating System (OS) requirements or the
     applicati...