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Bit Rotator with Minimum Wire Resistive Capacitive Delay for Bit Interleave Data

IP.com Disclosure Number: IPCOM000118002D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 218K

Publishing Venue

IBM

Related People

Ji, J: AUTHOR [+2]

Abstract

Disclosed is a bit rotator for data with interleave bits. The disclosed rotator takes advantage of the interleave bits to minimize the Resistive Capacitive (RC) delay of the wire. It also reduces the number of wire tracks required to the minimum. Thus, it makes the rotator faster and smaller. A 64b bit rotator will be used to demonstrate the design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Bit Rotator with Minimum Wire Resistive Capacitive Delay for Bit
Interleave Data

      Disclosed is a bit rotator for data with interleave bits.  The
disclosed rotator takes advantage of the interleave bits to minimize
the Resistive Capacitive (RC) delay of the wire.  It also reduces the
number of wire tracks required to the minimum.  Thus, it makes the
rotator faster and smaller.  A 64b bit rotator will be used to
demonstrate the  design.

      As the transistor gets smaller and faster, the RC delay of the
wire plays a more important role in the total delay of a design.  How
smaller components are wired will affect the RC delay significantly.

      In general, a 64b bit rotator requires 6 control bits, S(0:5),
to dictates the number of bits to be rotated.  When 4w MUX's are
used, a 64b bit rotator is implemented in 3 rows.  The first row,
controlled by  S0 and S1, rotates groups of 16.  The second row,
controlled by S2 and  S3, rotates groups of 4.  The third row,
controlled by S4 and S5, rotates  groups of 1 bit.  The longest wires
in the rotator are the ones which have to traverse from 1 end of the
rotator to the other end.  For example, MUX 63 in the 3rd row selects
either bit 63, 0, 1, or 2. Bit  0, 1, and 2 require long wires to
connect from MUX 0 to MUX 63.

      When a machine works on word boundary and the data flow is 64
bits, bit interleave is used.  Fig. 1 demonstrates a 64-bit data with
bit interleave.  For bit interleave data, the rotation should be
handled differently to minimize the interconnect wires.

      The proposed rotator takes advantage of the interleave
bits.  It's also implemented in 3 rows of 4w MUX's.  However, the
first row, controlled by S1 and S2, rotates groups of 8.  The second
row, controlled by S3 and S4, rotates groups of 2.  The third row,
controlled by S0 and S5, rotates either 1 or 32.  Fig. 2 shows some
of the left side  MUX's of the rotator.  The wiring of the control
bits is not shown. MUX0  of the first row selects either data bit 0,
8, 16, or 24.  The rest of  first row also select data in that order.
MUX0 of the second row selects  data bit 0, 2, 4, or 6, coming out
from the first...