Browse Prior Art Database

Improved BUS Interface between a Neural Network and a Personal Computer Parallel Input/Output Port (Industry Standard Architecture or Micro Channel)

IP.com Disclosure Number: IPCOM000118008D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Louis, D: AUTHOR [+2]

Abstract

The handshaking between the Personal Computer (PC) bus and the slave device is performed by the Input/Output (IO) Read(IOR_) or IO Write(IOW_) PC bus out signal and the WAIT_ signal generated by the slave device, the neural network. The IOR_ and IOW_ signals are "ANDed" on card to generate the AS_ (address strobe) and DS_ (data strobe) signals used by the neural network in order to offer a multi-bus connection.

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Improved BUS Interface between a Neural Network and a Personal Computer
Parallel Input/Output Port (Industry Standard Architecture or Micro
Channel)

      The handshaking between the Personal Computer (PC) bus and the
slave device is performed by the Input/Output (IO) Read(IOR_) or IO
Write(IOW_) PC bus out signal and the WAIT_ signal generated by the
slave device, the neural network.  The IOR_ and IOW_ signals are
"ANDed" on card to generate the AS_ (address strobe) and DS_ (data
strobe) signals  used by the neural network in order to offer a
multi-bus connection.

      Since the neural network runs much faster than the bus but
needs, for some operations, several machine cycles (1 cycle = 40 ns),
a pipelined protocol scheme has been introduced for the write
operation.  The idea is to acknowledge a write cycle as soon as the
strobes, address and data have been latched into the network, even if
the processing of the data is not yet finished (some operations can
take up to 20 machines cycles in the worst case).  With this fast
acknowledgement, the PC bus is liberated as soon as possible in order
to let the master processor perform other operations.  If the master
accesses again the neural network just after a first access, the
previous operation could not be terminated.  To avoid destroying the
previous operation by the new operation, a BUSY signal is generated
in the slave device to freeze the bus.  That means the new operation
is upheld on the bus because it is not acknowledged until the first
operation is completed.  This scheme is similar to a decode and
execute stage of a processor but without execute stage as shown in
the Figure.

      Now referring to the Figure, the circuit outside...