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Design for Testability that Avoids Bus Contention

IP.com Disclosure Number: IPCOM000118018D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Savir, J: AUTHOR

Abstract

Current practice in some product line tests creates bus contention when the test generator (FastScan, for example) tries to propagate fault effects through the bus. The test generator computes patterns that try to pull the bus in opposite directions. Since these patterns are invalid, the test generator has to throw them away and try to compute new patterns. A lot of test generation effort is put on this task, as well as many man-hours to filter out the problem. The present invention will avoid this problem altogether by a special design.

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Design for Testability that Avoids Bus Contention

      Current practice in some product line tests creates bus
contention when the test generator (FastScan, for example) tries to
propagate fault effects through the bus.  The test generator computes
patterns that try to pull the bus in opposite directions.  Since
these patterns are invalid, the test generator has to throw them away
and try  to compute new patterns.  A lot of test generation effort is
put on this  task, as well as many man-hours to filter out the
problem.  The present  invention will avoid this problem altogether
by a special design.

      Fig. 1 shows the affected logic.  Test patterns are fed in
through the scan chain.  When the system clocks are activated, these
patterns propagate through the logic.  Depending on which drivers
(D1, D2, Dn) are enabled (enable lines not shown), opposite values
may be attempted to feed the bus (for example D1 tries to write a
"1", while D2 tries to write a "0").  When this happens, the computed
test vector is invalid, and the test generator needs to try to
compute a different set of patterns.

      Fig. 2 shows the proposed solution to the problem.  Assume
that a value of "1" should win over a value of "0" in presence of bus
contention.  A number of AND gates, an OR gate and a DRIVER (D) have
been added to the logic.  In test mode (TM=1) all the normal drivers
(D1 to Dn) are de-activated and the logic can write into the bus via
a single wire.  S...