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Frame Buffer Architecture using Split Bank Update

IP.com Disclosure Number: IPCOM000118059D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Brase, D: AUTHOR [+4]

Abstract

The frame buffer mapping technique described in the article allows memory that is multiplexed to the Random Access Memory Digital to Analog Converter (RAMDAC) to also be used in a non-multiplexed fashion. This allows the same Frame Buffer architecture to cover multiple design points. The Frame Buffer can provide a high pixel depth but lower resolution using multiplexing of memory or lower pixel depth but higher screen resolution using non-multiplexed memory.

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This is the abbreviated version, containing approximately 52% of the total text.

Frame Buffer Architecture using Split Bank Update

      The frame buffer mapping technique described in the article
allows memory that is multiplexed to the Random Access Memory Digital
to Analog Converter (RAMDAC) to also be used in a non-multiplexed
fashion.  This allows the same Frame Buffer architecture to cover
multiple design points.  The Frame Buffer can provide a high pixel
depth but lower resolution using multiplexing of memory or lower
pixel depth but higher screen resolution using non-multiplexed
memory.

      The Frame Buffer interface to the RAMDAC may be smaller than
desired due to RAMDAC pin limitations.  The Figure shows a frame
buffer that is capable of 24 bits per pixel in high resolution
(1280x1024).  A workstation architecture is used in the example which
provides up to 24 bits per pixel.  The pixel data is mapped such that
each bank contains a different color band of a true color 24 bit
pixel.  The first bank would contain only Red color bands of 8 bit
depth.  The second would contain Green and the third Blue color
bands.  Each memory bank (three memory banks are shown in the Figure)
can be thought of as having 64 bits of input and 64 bits of output.
The Graphics Controller has 64 bits of data connected in parallel to
each bank.  The Figure shows two data buses, A and B, that would each
provide 32 bits of pixel data.  The full output of the frame buffer,
3x64=196 bits, is beyond the interface of available RAMDAC chips.
The interface of each bank to the RAMDAC is reduced by half by
connecting the two halves of each bank to the same 32 bits of RAMDAC
interface.  This provides a 2:1 multiplexing function, with the
correct use of Video Random Access Memory (VRAM) output enables.  The
example system would provide four 24 bit pixels in parallel to the
RAMDAC and require 96 data pins.  Given current VRAM serial port
capability this design will support resolutions up to approximately
1280x1024.  The system shown in the Figure, however, presents some
problems when larger resolutions are considered.

      A higher resolution monitor, 1600x1280, requires a much faster
operating frequency.  The faster frequency can exceed the capability
of the VRAM devices when the 2:1 multiplexing is employed.  The
memory size required to contain the larger resolution may also be
beyond the capacit...