Browse Prior Art Database

Support of G.706 Requirements for Primary Integrated-Services Digital Network Homologation

IP.com Disclosure Number: IPCOM000118064D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 109K

Publishing Venue

IBM

Related People

Benayoun, A: AUTHOR [+4]

Abstract

Before connecting a primary Integrated Service Digital Network (ISDN) adapter to a network, it has to be homologated by the telecommunication approval center of the country. One of the tests performed is the compliance to the G.706 International Telegraph and Telephone Consultative Committee (CCITT) recommendations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Support of G.706 Requirements for Primary Integrated-Services Digital
Network Homologation

      Before connecting a primary Integrated Service Digital Network
(ISDN) adapter to a network, it has to be homologated by the
telecommunication approval center of the country.  One of the tests
performed is the compliance to the G.706 International Telegraph and
Telephone Consultative Committee (CCITT) recommendations.

A primary ISDN adapter is made of four major hardware components:
  1.  a Line Interface Unit chip for the network electrical
       interface
  2.  a framer chip for the network framing protocol
  3.  a 32"channel High"Data Link Control controller
  4.  a microprocessor to run the ISDN code

The G.706 requirements apply to the framer and its associated code.
The following functions are verified:
  o  frame alignment
  o  multiframe alignment
  o  Cyclic Redundancy Check (CRC)"4 error detection

Hardware Implementation

      To optimize the microprocessor performance, the interrupt mode
has been chosen to the polling mode.  A specific hardware has been
implemented in a PAL between the framer and the microprocessor.  The
Figure describes the involved piece of hardware.

      This design is using an 80188-16MHz microprocessor, a Bt8510
framer and a 22V10 PAL.  When activated, the timer generates a 1ms
clock to monitor each subframe of the multiframe.

The equation of the PAL is given hereafter.
  ;PALASM Design Description
  ;---------------------------- Declaration Segment ------------
  TITLE    NMI Generation for G.706
  PATTERN
  REVISION
  AUTHOR
  COMPANY
  DATE
  CHIP     Reference PAL22V10
  ;---------------------------- Inputs -------------------------
  PIN  1     CLK       ; Microprocessor clock
  PIN  2     INT  ...