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Browse Prior Art Database

Echo Clock for Microprocessor - Static Random Access Memory Interface

IP.com Disclosure Number: IPCOM000118069D
Original Publication Date: 1996-Sep-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Lattimore, GM: AUTHOR [+2]

Abstract

Interfaces between cache systems and microprocessors need to continue to increase in frequency as microprocessor performances increase. However, there has been little change in the actual system environment to allow the cache system interface to continue to increase its performance. Somewhere around 200 - 250 Mhz is the frequency limit of a traditional synchronous cache system interface with a microprocessor. This limit is determined by a number of parameters including both packaging and device. Some of the packaging variables that can influence this are the package type, number of cache chips, width of dotting on buses, and density of cache chip packaging. The device parameters include cache access time, processor clock to queue time and processor and cache chip setup and hold times.

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This is the abbreviated version, containing approximately 52% of the total text.

Echo Clock for Microprocessor - Static Random Access Memory Interface

      Interfaces between cache systems and microprocessors need to
continue to increase in frequency as microprocessor performances
increase.  However, there has been little change in the actual system
environment to allow the cache system interface to continue to
increase its performance.  Somewhere around 200 - 250 Mhz is the
frequency limit of a traditional synchronous cache system interface
with a microprocessor.  This limit is determined by a number of
parameters including both packaging and device.  Some of the
packaging variables that can influence this are the package type,
number of cache chips, width of dotting on buses, and density of
cache chip packaging.  The device parameters include cache access
time, processor clock to queue time and processor and cache chip
setup and hold times.  In summary, the processor frequencies are
increasing at the fastest rate with cache operating frequencies
lagging slightly.  Improvement in cache access times and interconnect
delays have been minor for an extended period of time and
breakthroughs in improvement for either do not seem to be on the
horizon.

      At present, private cache implementations are
synchronous.  Each time an address is sent to the cache it is known
that data will return after N cycles.  With these implementations, a
form of  cycle stealing can take place between the processor and the
cache. For  instance, the phase of the cache clock is often not the
same as the phase of processor clock.  The clock is phase shifted as
it is sent from the processor to the cache in order to meet signal
set up and hold  time at the cache and maximize timing margins when
data is sent back.

      The performance of a synchronous interface is limited by the
requirement that signals must be launched and captured at specific
points during a cycle, usually on cycle boundaries.  A more flexible
and robust interface can be designed if the cache chips send a clock
back with their data to the microprocessor.  This helps solve the
problem of differing delay times for addre...