Browse Prior Art Database

Clock and Signal Repowering for Submicron Very Large Scale Integration

IP.com Disclosure Number: IPCOM000118075D
Original Publication Date: 1996-Sep-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Aipperspach, TG: AUTHOR [+9]

Abstract

Disclosed is a clock and signal repowering technique.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Clock and Signal Repowering for Submicron Very Large Scale Integration

      Disclosed is a clock and signal repowering technique.

      Modern integrated circuits are increasingly affected by wire
delays as opposed to circuit delays.  A current solution is to use
fat wires extensively, yet this takes up considerable wire space
making other routing difficult or impossible.  Another solution is to
insert buffers in long wires in exact locations, but this could
impact the quality of chiplet design.

      The solution has several parts.  One is to explicitly lay out
a clock "spine" in the chip reserved for clocks repowering.  This is
to assist clock skew from the very start.
        ************
        *    C     *
        *    C     *
        *    C     *
        *    C     *
        *    C     *
        *    C     *
        *    C     *
        *    C     *
        ************

      Another part is the special layout of a repowering circuit such
that it is completely wireable from any wire crossing over it.  (This
is possible at little or no density impact).  Examples are shown
below:
        ***************     ***************  where I - input pin
        *  I    O     *     *             *        O - output pin
        *  I    O     *     *IIIIIIIIIIIII*
        *  I    O     *     *             *
        *  I    O     *     *             *
        *  I    O     *     *             *
        *  I    O     *     *             *
        *  I    O     *     *OOOOOOOOOOOOO*
        *  I    O     *     *             *
        ***************     ***************

      The  wiring then proceeds in a top-down fashion with the long
signals and clocks put in first.  This way, long critical nets known
from the beginning are given priority.  Long nets which do not meet
timing...