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Circuit Means to Shut Off Direct Current Flow for Supply Current Test

IP.com Disclosure Number: IPCOM000118086D
Original Publication Date: 1996-Sep-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Cao, T: AUTHOR [+4]

Abstract

An important manufacturing test for microprocessor and other Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integration (VLSI) devices is a current leakage test. This test is performed at both the wafer level and packaged chip level. This test has been shown to be a good means to eliminate devices that will have short lifetimes. With this test, the manufacturer can establish a leakage current limit above which the chip will be rejected.

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Circuit Means to Shut Off Direct Current Flow for Supply Current Test

      An important manufacturing test for microprocessor and other
Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale
Integration (VLSI) devices is a current leakage test.  This test is
performed at both the wafer level and packaged chip level.  This test
has been shown to be a good means to eliminate devices that will have
short lifetimes.  With this test, the manufacturer can establish a
leakage current limit above which the chip will be rejected.

      Applying this test to the CMOS driver/receiver circuit shown
in Fig. 1 is problematic because certain portions of the circuit
(designated as areas 1 through 3 in the Figure) provide a Direct
Current (DC) path to ground.

      Area #1 is the reference voltage generator, area #2 is the
differential amplifier output clamp to ground, and area #3 is the
differential amplifier output clamp to supply voltage.  DC current
paths in areas 1 through 3 of Fig. 1 are eliminated as described
herein.

      Fig. 2 shows the improved schematic which no longer has the
three DC current paths from supply voltage to ground during supply
current test.

      The data inputs to the circuit are a differential pair labeled
RIN and RIN_.  There is also a gate input labeled RINH_ .  When RINH_
is a "1", the circuit outputs ROUT and ROUT_ are set to the data in
states of RIN and RIN_, respectively.  This would be a normal data
flow operati...