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Browse Prior Art Database

Mechanism for Scan-Based Test Application at High-Speed

IP.com Disclosure Number: IPCOM000118088D
Original Publication Date: 1996-Sep-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 8 page(s) / 248K

Publishing Venue

IBM

Related People

Dillinger, TE: AUTHOR [+2]

Abstract

Disclosed is a design technique for an asynchronous scan interface between a Device Under Test (DUT) and the tester applying test pattern stimulus and receiving DUT responses. This technique is based upon the current approaches of "reduced pin-contact testing" and scan-based design for testability structures incorporated into the DUT. It differs from current methods in that the tester is not controlling the clocks applied to the DUT. Rather, an asynchronous protocol is described between DUT and tester, which enables the transmission of stimulus and responses at data rates less than the internal operation frequency of the DUT.

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This is the abbreviated version, containing approximately 29% of the total text.

Mechanism for Scan-Based Test Application at High-Speed

      Disclosed is a design technique for an asynchronous scan
interface between a Device Under Test (DUT) and the tester applying
test pattern stimulus and receiving DUT responses.  This technique is
based upon the current approaches of "reduced pin-contact testing"
and scan-based design for testability structures incorporated into
the DUT.  It differs from current methods in that the tester is not
controlling the clocks applied to the DUT.  Rather, an asynchronous
protocol is described between DUT and tester, which enables the
transmission of stimulus and responses at data rates less than the
internal operation frequency of the DUT.

      Current testing fixtures do not permit pattern application
rates anywhere close to the intended clock frequency of
microelectronic designs.  As a result, at-speed chip failures may
pass at the tester.

      On-chip Built-In-Self-Test (BIST) networks have recently been
added to microelectronic designs, and can help to uncover at-speed
failures.  Yet, the tester interface still commonly uses a set of
tester-applied clocks to control the on-chip BIST circuitry.

      Very high-performance chip designs use a single free-running
clock, with a highly tuned generation and distribution method on-chip
to minimize edge arrival skews at the clock loads.  Introduction of
test clocks into the clock generation network deleteriously perturbs
this design, adding to the arrival skews in functional mode.

      The technique to be described eliminates the need for tester
clocks, enhancing the ability to perform at-speed testing with a
highly optimized clock signal generated internally by the DUT.  The
additional overhead circuitry required of the DUT and the tester is
minimal.

The philosophy behind this technique is that:
  o  the interface between DUT and tester is completely asynchronous
  o  all events are initiated by an edge transition on one of the
      interface signals
  o  all signal protocol events involve both a request and
      acknowledge pair of transitions between DUT and tester;
      failure to receive an acknowledge signal in the test sequence
      should be regarded as an invalid response
  o  asynchronous inputs to the DUT will be synchronized
      to the internal functional clock using an appropriate
      low-metastability synchronizer design (not shown)

      A block diagram of the interface between DUT and tester is
provided in Fig. 1.  Four signals define the asynchronous interface:
  o  Test Mode Select (TMS):  selects test mode, as opposed to
      functional mode
  o  Test Control Signal (TCS):  used to initiate pattern data
      transfer from the tester to the DUT, and to acknowledge receipt
      of DUT response
  o  Tester Feedback Signal (TFS):  like TCS, but driven from
      the DUT; used to initiate data transfer from DUT, and...