Browse Prior Art Database

Family of Bus Protocols to Enable Timesharing Between Miss Transactions

IP.com Disclosure Number: IPCOM000118090D
Original Publication Date: 1996-Sep-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Bose, P: AUTHOR [+3]

Abstract

In current bus protocols, when a processor issues a miss request, it sends the following three pieces of information to the memory hierarchy: 1. Address (real) of the datum that is to be returned first (and thereby, explicitly, the address of the line that contains the datum), 2. A Miss ID which (on a shared bus system) comprises 2 parts: a. The ID of the processor that is issuing the miss, and b. The ID of the miss (in case the processor can have more than one miss outstanding), 3. The Miss Type tells the memory what status is needed for the line (e.g., shared, exclusive, etc.).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Family of Bus Protocols to Enable Timesharing Between Miss Transactions

      In current bus protocols, when a processor issues a miss
request, it sends the following three pieces of information to the
memory hierarchy:
  1.  Address (real) of the datum that is to be returned first
       (and thereby, explicitly, the address of the line that
       contains the datum),
  2.  A Miss ID which (on a shared bus system) comprises 2 parts:
      a.  The ID of the processor that is issuing the miss, and
      b.  The ID of the miss (in case the processor can have more
           than one miss outstanding),
  3.  The Miss Type tells the memory what status is needed for
       the line (e.g., shared, exclusive, etc.).

When modern memory systems return data, they send back the second
field above with the data.  This is the way that the processors on
the bus can tell what the data is (i.e., who it is for, and what miss
it corresponds to).

      These protocols treat an entire miss as a "transaction," and
they lock up the bus for the duration of the line transfer.  For
these protocols, the second field (above) need not be sent back on
every bus  cycle, it is just sent at the beginning of each
transaction.  In a new family of bus protocols, every bus cycle is
treated as a unique transaction, and the second field (above) is sent
on every cycle to identify the data for that cycle.

      This family of protocols has as many as 3 additional control
fields that are sent with each miss request.  Each field is optional,
and each can be arbitrarily simple or complex.  The fields are:
  1.  A Priority Level is used to distinguish as many of the
following
       types of misses as desired:
      o  Demand Data Fetch (exigent)
      o  Demand Instruction Fetch (exigent)
      o  Demand Data Fetch down conditional path (conditionally
          exigent)
      o  Demand Instruction Fetch down conditional path
          (conditionally exigent)
      o  Data Fetch down speculative path (speculatively exigent)
      o  Instruction Fetch down speculative path (speculatively
          exigent)
      o  Data Prefetch initiated by prefetch mechanism (prefetch)
      o  Instruction Prefetch initiated by prefetch mechanism
          (prefetch)
  2.  Multiplex Control specifies how this data stream is
       to be multiplexed with respect to the other active
       streams.  Assuming that Field #1 (above) is not used,
       Field #2 might specify one of the following actions:
      o  Put the entire stream behind the currently active traffic.
          (This is the current default, i.e., this is what current
          protocols do.)
      o  Suspend all other active traffic for one bus cycle to
          return the first datum from this miss immediately, then
 ...