Browse Prior Art Database

Gathering Store Instructions in a Superscalar Processor

IP.com Disclosure Number: IPCOM000118096D
Original Publication Date: 1996-Sep-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 86K

Publishing Venue

IBM

Related People

Pekkala, R: AUTHOR [+3]

Abstract

Disclosed is a method for obtaining better store instruction performance in a superscalar processor by combining various store instructions to the same doubleword address into a single cache access.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Gathering Store Instructions in a Superscalar Processor

      Disclosed is a method for obtaining better store instruction
performance in a superscalar processor by combining various store
instructions to the same doubleword address into a single cache
access.

      After a store instruction has been translated, it is put into
the Finished Store Queue (FSQ) where it will reside until it obtains
the data from the General Purpose Registers (GPRs).  At this point,
the stores are added to the FSQ in program order and interrupt status
has been reported.  Once in the FSQ, a mask is generated in order to
tell the cache which bytes of the line to write (these are the actual
write-enables for the cache).  Once the store data is obtained from
the GPRs and the sequencer has determined that the store operation is
non-speculative, then the store is put into the Committed Store Queue
(CSQ).  The CSQ also contains the byte masks, the necessary opcode
information, and the data.

      In a microprocessor that contains separate load and store
pipelines, the arbitration for access to the cache will always favor
the loads since these instructions are generally more dependent upon
by other instructions.  The problem this creates is that the store
queue will contain many stores that are waiting to be written to the
cache for many cycles.  Thus, the store queue may fill up quickly or
need to be very large.  Furthermore, there is a necessity to reduce
bus traffic in low-cost s...