Browse Prior Art Database

Self-Aligned Protection of Cu for Flat Panel Display Wiring Applications

IP.com Disclosure Number: IPCOM000118131D
Original Publication Date: 1996-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 101K

Publishing Venue

IBM

Related People

Batey, J: AUTHOR [+5]

Abstract

Lower resistivity conductors are needed for flat panel display applications as the size and number of pixels increases. The data/gate line length and data rates will be limited by the currently used metallurgies (Mo, Ta, or mixtures there of, about 12-40 mu-ohms). Reducing the line resistance by increasing the width of the lines is undesirable because the aperture ratio of the display is reduced and increasing the thickness of the lines is undesirable because step coverage of subsequent layers becomes difficult. The only way to achieve the required line resistance within the allowable dimensions is to change the conductor material. The lowest resistance material, which would be economically viable to use, is Cu.

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Self-Aligned Protection of Cu for Flat Panel Display Wiring Applications

      Lower resistivity conductors are needed for flat panel display
applications as the size and number of pixels increases.  The
data/gate line length and data rates will be limited by the currently
used metallurgies (Mo, Ta, or mixtures there of, about 12-40
mu-ohms).  Reducing the line resistance by increasing the width of
the lines is undesirable because the aperture ratio of the display is
reduced and increasing the thickness of the lines is undesirable
because step coverage of subsequent layers becomes difficult.  The
only way to achieve  the required line resistance within the
allowable dimensions is to change the conductor material.  The lowest
resistance material, which would be economically viable to use, is
Cu.

      There have been significant efforts recently on using Cu
metallizations for VLSI multilevel interconnects in the integrated
circuit industry.  Patents have been issued for adding alloy
additions to Cu which segregate and form an oxide layer at the
surface of Cu features to provide oxidation protection and adhesion
(1,2) or which segregate and form a nitride layer for oxidation
protection (3).  A recent publication described alloying Cu with Si,
and forming a SiO(2)  surface layer after annealing in an oxidizing
ambient (4).  An alternate  approach, which does not involve
depositing a Cu alloy, based on a selective reaction has also been
patented (5).  In this process, after  the Cu is patterned a blanket
metal layer (such as Ti) is deposited, reacted with the Cu to form
intermetallic compounds, selectively etched  to remove the unreacted
Ti from field areas, and annealed in NH(4) to form a protective TiN
layer.  All of these methods result in a self-aligned layer on the Cu
to provide oxidation protection.

      The processes used to fabricate flat panel displays are
significantly different from those used in integrated circuit
manufacturing, so the requirements a Cu passivation layer must meet
are different.  With FPDs the area being processed for each device is
extremely large and pin-holes in insulating layers become a key
concern because wet etching is typically used to pattern subsequent
conducting layers.  For example, after the Cu gate line is fabricated
a thin (about 300 nm) Si(3)N(4) is all that protects it from attack
during Indium-Tin Oxide (ITO) etch (Hydrochloric/Nitric/water) and
data metal etch (Phosphoric/ Acetic/Nitric/water).  If no additional
passivation is present on the Cu, either of these etches can result
in open lines at pin holes in the Si(3)N(4) where the Cu is attacked.
This can produce a line open and reduced yield.  For a manufacturable
process...