Browse Prior Art Database

Data Transfer Between CPU and Input/Output Device

IP.com Disclosure Number: IPCOM000118148D
Original Publication Date: 1996-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Kimura, T: AUTHOR

Abstract

Disclosed is a method for Input/Output (I/O) device and CPU access. This method uses X bit CPU and I/O device which is bigger than X bit. This way data can be transferred on X bit data bus, using memory device and simple hardware. Using this Method hardware consists of X bit CPU(4), Y bit I/O device(1) and Y bit memory device(2). I/O device, memory device and data selector are connected with Y bit data bus(4) (Figure). This method describes read and write functions for CPU and I/O device as follows:

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Data Transfer Between CPU and Input/Output Device

      Disclosed is a method for Input/Output (I/O) device and CPU
access.  This method uses X bit CPU and I/O device which is bigger
than X bit.  This way data can be transferred on X bit data bus,
using memory device and simple hardware.  Using this Method hardware
consists of X bit CPU(4), Y bit I/O device(1) and Y bit memory
device(2).  I/O device, memory device and data selector are connected
with Y bit data bus(4) (Figure).  This method describes read and
write functions for CPU and I/O device as follows:

      (a) In the write case of I/O device, first X bit data is
transferred from CPU to some memory area.  Repeat transfer to more
memory area, Y bit data is transferred from memory device to I/O
device on one time.  (b) The read case of I/O device is opposite to
the write case.  In this method it is unnecessary to latch logic
hardware for I/O device.

      There are some applications by using this method which is
accessed data from 8 bit cpu to 16 bit I/O.