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Hardware Performance Trace Enhancement to Include Performance Events

IP.com Disclosure Number: IPCOM000118153D
Original Publication Date: 1996-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Larsen, TR: AUTHOR [+2]

Abstract

Disclosed is an economical method to include selectable performance event data in hardware address and instruction traces. The internal performance monitor counter logic is used to select events to be included in the hardware traces. The events selected are latched and included in the hardware trace. The latches are reset when a trace entry is generated; therefore, the additional event signals indicate if the selected event has occurred since the last trace entry.

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Hardware Performance Trace Enhancement to Include Performance Events

      Disclosed is an economical method to include selectable
performance event data in hardware address and instruction traces.
The internal performance monitor counter logic is used to select
events to  be included in the hardware traces.  The events selected
are latched and  included in the hardware trace.  The latches are
reset when a trace entry  is generated; therefore, the additional
event signals indicate if the selected event has occurred since the
last trace entry.

      The disclosure uses the performance monitor counter facility in
conjunction with the performance trace facility to give additional
performance information about the trace data being taken.  For
example, additional details about each trace entry can be monitored
by the programmable counter facility and included with the trace
data.  The performance monitor counter facility is fully software
programmable for  events to count, so the content of the correlation
data can be changed  based on what additional information is desired,
or based on trace type,  i.e., different information would be wanted
for each different type of  address or instruction trace.

      As shown in the Figure, hundreds of performance events are
available within the processor for monitoring various aspects of
performance.  The performance monitor control registers select which
events are to be counted by the performance monitor counter...