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Bidirectional Queue Register for Cache Line Reads and Writes Between Asynchronous Timing Boundaries

IP.com Disclosure Number: IPCOM000118177D
Original Publication Date: 1996-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Edwards, JM: AUTHOR

Abstract

Typically, Input/Output (I/O) channels on processor complexes are architecturally different from the processor's memory bus. As memory transfer occur between the I/O and the processor's memory, there must be some means of pacing the cache line reading and writing between the I/O and the processor memory. Queueing the requests of the I/O channel in either hardware or software is typical.

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Bidirectional Queue Register for Cache Line Reads and Writes Between
Asynchronous Timing Boundaries

      Typically, Input/Output (I/O) channels on processor complexes
are architecturally different from the processor's memory bus.  As
memory transfer occur between the I/O and the processor's memory,
there must be some means of pacing the cache line reading and writing
between the I/O and the processor memory.  Queueing the requests of
the I/O channel in either hardware or software is typical.

      Disclosed is a simple, yet extendable algorithm for determining
whether an outstanding cache line request is pending for asynchronous
bus.  The basic mechanism is a bidirectional shift register.  The
number of bits in the shift register corresponds to the number of
outstanding requests that can be queued (Figure).  Binary 1's are
shifted in from the left as cache line requests are issued, and
binary 0's are shifted in from the right as cache lines requests are
serviced.  If a cache line is serviced simultaneously with a cache
line being requested, then the shift register is held in its present
state.  An observation of the leftmost bit is an indicator to a cache
line request controller that a cache line must be fetched or written
to the processor memory (binary1).  An observation of the rightmost
bit in the shift register is an indicator to the I/O bus controller
that more requests can be issued (binary0).  The algorithm can be
implemented identically by shiftin...