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# Gated Clock Removal Algorithm

IP.com Disclosure Number: IPCOM000118179D
Original Publication Date: 1996-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 82K

IBM

Earl, JR: AUTHOR

## Abstract

Disclosed is a method of replacing a gated clock signal in a digital logic circuit with a multiplexor and a feedback path.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Gated Clock Removal Algorithm

Disclosed is a method of replacing a gated clock signal in a
digital logic circuit with a multiplexor and a feedback path.

The first step in understanding this algorithm is to convince
yourself that clock gating can be replaced by a multiplexor on the
data input (Fig. 1).

The purpose of a gated clock is to allow some "enable" signal
to force a latch to maintain the same output regardless of clock
activity.  This same goal can be implemented with a free-running
clock if the "enable" signal is used to select whether the data input
of the  latch is fed with new data or with "old data" - the latch's
output.

In general cases, the AND gate can be a gate of arbitrary
function.  Since this gate likely drives other inputs besides the one
we are trying to unclock, a copy is made, and the connections to the
copy are modified to suit our needs (Fig. 2).

The clock gate's Boolean function is checked to make sure that
the clock signal can be factored out.  If it cannot, the algorithm
cannot be applied.  This should not happen ordinarily, since a
non-factorable clock signal implied that the data signal(s) could
clock the register.  Provided that the clock can be factored out of
the gating function F, the clock signals to the clock gate copy can
be replaced by a constant corresponding to the active state of the
clock to generate a function F' that when ANDed with the clock is
identical to the original...