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Tape Ball Grid Array Lead Design to Optimize Manufacturing and Assembly Yield

IP.com Disclosure Number: IPCOM000118192D
Original Publication Date: 1996-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Bhatt, AC: AUTHOR [+4]

Abstract

As feature dimensions in the electronic packaging field continue to shrink, manufacturing of smaller dimensions becomes more difficult to accomplish. Requirements for inner lead dimensions on Tape Ball Grid Array (TBGA) packages are shrinking to match the Input/Output (I/O) requirements of the chips to which they are bonded. However, manufacturing yields for the TBGA carrier suffer as these dimensions become smaller, due to the limitations inherent in the imaging and photolithography steps in the process. In addition, as the inner leads, which form cantilever beams, shrink in dimension, their inherent fatigue reliability decreases.

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Tape Ball Grid Array Lead Design to Optimize Manufacturing and Assembly
Yield

      As feature dimensions in the electronic packaging field
continue to shrink, manufacturing of smaller dimensions becomes more
difficult to accomplish.  Requirements for inner lead dimensions on
Tape Ball Grid Array (TBGA) packages are shrinking to match the
Input/Output (I/O) requirements of the chips to which they are
bonded.  However, manufacturing yields for the TBGA carrier suffer as
these dimensions become smaller, due to the limitations inherent in
the imaging and photolithography steps in the process.  In addition,
as the inner leads, which form cantilever beams, shrink in dimension,
their inherent fatigue reliability decreases.

      In manufacturing TBGA carrier, yield advantages are realized
by keeping line and inner lead widths as large as possible for a
given lead pitch requirement.  This conflicts with the assembly
requirement that the lead width must be smaller than the chip bump
width.

      The Figure shows how the carrier yield can be maximized and the
lead width in the Critical Chip Bonding Area (1) can be met by making
the most of the line width at a larger, more manufacturable dimension
(2), and decreasing the line width in the local vicinity of the chip
bump connection.  Reliability of the cantilever beams (3) is also
maximized with this design.