Browse Prior Art Database

Parallel Decode in a Set-Associative Cache for Enhanced Performance

IP.com Disclosure Number: IPCOM000118193D
Original Publication Date: 1996-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Venkatramani, J: AUTHOR

Abstract

The decoder in an in-line (AKA serial) cache controller determines the actions the cache controller must take on behalf of CPU-initiated requests or snoop requests. These actions depend on the type of bus transaction, and the cache status (HIT/MISS, cache state) of the affected block. This decoder is quite complex, especially, if the cache and the bus are designed to support a cache-coherent, shared memory, multi-processor system. The Table shows an example of a decode table and the resulting cache actions. In a set-associative cache, the cache status can be determined only after the identification of the element within the set. For example, in a 2-way set associative cache, the cache status can be either from way 0 or way 1 and this depends on which way was selected on a miss or a hit.

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Parallel Decode in a Set-Associative Cache for Enhanced Performance

      The decoder in an in-line (AKA serial) cache controller
determines the actions the cache controller must take on behalf of
CPU-initiated requests or snoop requests.  These actions depend on
the type of bus transaction, and the cache status (HIT/MISS, cache
state) of  the affected block.  This decoder is quite complex,
especially, if the  cache and the bus are designed to support a
cache-coherent, shared memory, multi-processor system.  The Table
shows an example of a decode  table and the resulting cache actions.
In a set-associative cache, the  cache status can be determined only
after the identification of the element within the set.  For example,
in a 2-way set associative cache,  the cache status can be either
from way 0 or way 1 and this depends on  which way was selected on a
miss or a hit.  Thus, the decode time can limit the speed of the
cache.

      This invention discloses a method for decode that allows for
higher speeds.  Since the cache status bits depend on the hit/miss
compare, it is usually valid late in the cycle.  However, the
transaction type and attributes are valid early in the cycle.  The
apparatus disclosed  here is illustrated in the Figure.  The cache
status bits from each element of the set (way 0 and way 1) are used
to decode multiple (A and  B) L2 actions.  Then, one of the decoded
L2 actions is selected by the  result of the hit/miss compare (C)...