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Complementary Switched Capacitor Circuit

IP.com Disclosure Number: IPCOM000118211D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Bechade, R: AUTHOR [+3]

Abstract

Disclosed are several methods of minimizing components and signal sources in clocked switched capacitor circuits.

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This is the abbreviated version, containing approximately 76% of the total text.

Complementary Switched Capacitor Circuit

      Disclosed are several methods of minimizing components and
signal sources in clocked switched capacitor circuits.

      Fig. 1 shows a common switched capacitor circuit.  NFETs Q1 and
Q2 are used to charge capacitor C alternately from voltage Va to
voltage Vb.  The voltages of nodes F1 and F2 are out-of-phase.  In
the first phase of a cycle, Q1 is conducting, Q2 is non-conducting,
and capacitor C is charged to the voltage Va.  In the second phase,
Q1 is non-conducting, Q2 is conducting, and C is charged to voltage
Vb.  Thus, each cycle Q1 and Q2 each conduct a charge Q equal to
C*(Va-Vb).  If the cycles occur with frequency f, the average current
through the series devices Q1 and Q2 is f*C*(Va-Vb).

      In order to ensure that Q1 and Q2 do not conduct
simultaneously, the controlling phases F1 and F2 must be
non-overlapping.

      Fig. 2 shows an improved switched capacitor circuit.  Q1 is a
p-channel FET and Q2 is an n-channel FET.  Assuming that Va-Vb is
less than the sum of the threshold voltages of Q1 and Q2, Q1 and Q2
will never conduct simultaneously during a clock transition.  There
are no timing constraints for this circuit.

      Fig. 3 shows a differential version for low noise
applications.  For this topology, coupling into Va and Vb through
parasitic gate to source/drain capacitance is cancelled by
complementary phases F1 and F2.

      Fig. 4 shows another version of the invent...