Browse Prior Art Database

High-Performance Frame Buffer Mapping for Multi-Media Graphics Systems

IP.com Disclosure Number: IPCOM000118221D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 6 page(s) / 243K

Publishing Venue

IBM

Related People

Johns, CR: AUTHOR [+2]

Abstract

Graphics adapters designed for a given maximum pixel size typically operate on smaller pixel sizes at the same performance level on a per pixel basis. For example, a 24 bit single buffer adapter will also typically support double buffered 8 bit and 12 bit modes of operations. The 8 bit and 12 bit modes will only use, at most, half of the available frame buffer bandwidth on updates. The other half is allocated to the other (non-updated) buffer. Disclosed is a logical-to-physical frame buffer mapping technique that can double the performance of a double buffer system by allowing all the available frame buffer bandwidth to be used in updating a single buffer.

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High-Performance Frame Buffer Mapping for Multi-Media Graphics Systems

      Graphics adapters designed for a given maximum pixel size
typically operate on smaller pixel sizes at the same performance
level on a per pixel basis.  For example, a 24 bit single buffer
adapter will also typically support double buffered 8 bit and 12 bit
modes of operations.  The 8 bit and 12 bit modes will only use, at
most, half of the available frame buffer bandwidth on updates.  The
other half is allocated to the other (non-updated) buffer.  Disclosed
is a logical-to-physical frame buffer mapping technique that can
double the performance of a double buffer system by allowing all the
available frame buffer bandwidth to be used in updating a single
buffer.

      A typical double buffered frame buffer would allocate half of
the data I/O to one buffer (i.e., front color buffer) and the other
half to the second buffer (i.e., back color buffer).  A common
situation is to map the first logical buffer into one physically
distinct bank of memory (Bank 0) and the second logical buffer into a
another physically distinct bank (Bank 1).  When updating one of the
logical buffers, only the data I/O to a single Bank would be active.

Fig. 2 Five pixel group mapping with order change every other row.

      The full data I/O may be utilized in updating either buffer by
toggling the mapping of first and second buffer between different
physical memory banks.  Fig. 1 illustrates this mapping.  The logical
to physical mapping alternates between odd and even pixel group
addresses.  If the rasterizer normally updates the frame buffer N
pixels at a time, then for the even addresses the first logical
buffer would be in Bank 0 and the second logical buffer in Bank 1.
For odd addresses the second logical buffer would be in Bank 0 and
the first logical buffer in Bank 1.  The rasterizer may then access
2N pixels for either logical buffer by offsetting the addresses to
the physical banks by one.  The alternation of logical to physical
mapping with pixel group address allows either logical buffer to be
accessed at full memory bandwidth for update and still allow both
logical buffers to be scanned out of the frame buffer simultaneously
for screen refresh.

      Take the example of a 24 bit single buffer system that accesses
the frame buffer 5 pixels at a time.  Fig. 2 shows the mapping
technique applied to this system.  In 8 bit and 12 bit double
buffered mode this system could access either buffer at 10 pixels at
a time.  Starting at address 0 the front buffer would be in physical
Bank 0 and the back buffer in Bank 1.  But for address 1 the back
buffer would be in Bank 0 and the front buffer in Bank 1.  The even
addresses would allocate the buffers as in address 0 and the odd
addresses as in address 1.  If the rasterizer was writing 20 pixels
to the front buffer starting at address 0, it could then complete
this operation in 2 cycles.  Bank 0 would receive...