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Method of Implementing Nap Mode in a PowerPC Multiprocessing System

IP.com Disclosure Number: IPCOM000118230D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Arroyo, RX: AUTHOR [+3]

Abstract

The process to enter Nap mode begins with software setting some register values in the processor and the memory controller. First, on a per processor basis, software initiates Nap mode by executing a code sequence (see the PowerPC* 604 User's Manual p. 4-21) which sets the Power management enable (POW) bit of the Machine Status Register. Once this bit is set, the corresponding CPU suspends instruction dispatch and waits for all active and pending transactions to finish. Upon completing these transactions, the 604 enters Doze mode by asserting its private HALT output and will then enter Nap mode by shutting down its clocks when the memory controller deasserts RUN. Then, software sets the Processor Nap Mode Enable bit of the 60x Arbiter Control Register of the memory controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Implementing Nap Mode in a PowerPC Multiprocessing System

      The process to enter Nap mode begins with software setting some
register values in the processor and the memory controller.  First,
on a per processor basis, software initiates Nap mode by executing a
code sequence (see the PowerPC* 604 User's Manual p. 4-21) which sets
the Power management enable (POW) bit of the Machine Status Register.
Once this bit is set, the corresponding CPU suspends instruction
dispatch and waits for all active and pending transactions to finish.
Upon completing these transactions, the 604 enters Doze mode by
asserting its  private HALT output and will then enter Nap mode by
shutting down its clocks when the memory controller deasserts RUN.
Then, software sets the Processor Nap Mode Enable bit of the 60x
Arbiter Control Register of the memory controller.  This alerts the
60x bus interface logic to monitor all of the system's HALT signals
and to place the system in Nap  mode under the appropriate
circumstances by deasserting the RUN output.

      The Figure illustrates the logic used by the 60x interface to
implement power management in an MP environment with the ultimate
goal of reaching the optimal system power-savings state of Nap mode.
The Figure is a Mealy state graph where input changes on the state
transitions result in updates on the output(s).  Note that a signal
in the graph preceded by a carat ("^") symbol is one that is
deasserted, while one without a carat represents a signal that is
asserted.  Also, note that the signal called HALT'S in the graph
refers to the condition where all of the HALT outputs in the system
are asserted, whereas if the signal is preceded by a carat symbol, it
indicates at least one processor is still in a Normal mode of
operation.

      While the system is in a Normal setting, the Figure shows the
60x interface logic will monitor the HALT signal from each processor.
If all of the HALT outputs are asserted, indicating the processors
want to enter Nap mode, the 60x logic will search its snoop queues to
det...