Browse Prior Art Database

Test and Debug Memory Cards Using a Programmable On-Chip Tester

IP.com Disclosure Number: IPCOM000118249D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Ruffner, H: AUTHOR [+3]

Abstract

Disclosed is a logic to test memory cards in manufacturing and/or in system at full system speed. The logic is integrated on the Storage Controller Chip (STC chip) of the memory card and can be used to test the Memory Array of itself or another memory card attached to it.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Test and Debug Memory Cards Using a Programmable On-Chip Tester

      Disclosed is a logic to test memory cards in manufacturing
and/or in system at full system speed.  The logic is integrated on
the Storage Controller Chip (STC chip) of the memory card and can be
used to test the Memory Array of itself or another memory card
attached to it.

      Testing memory cards for mainframe computers requires very
fast, high bandwidth testers.  This test equipment is extremely
expensive because it must be faster than the Device Under Test (DUT),
so that data  delivered by the DUT at system speed can be checked for
correctness. For  each new card design, the test equipment has to be
updated.

      To avoid high tester costs, DRAM and SRAM memory in earlier
designs have been tested with a built in, hardwired selftest.  This
selftest capability had significant disadvantages due to its lack of
flexibility, resulting in test coverage problems.  To enhance the
built in selftest capability, a programmable tester logic has been
implemented on the STC chip.  This ensures that the tester always
matches the voltage and speed requirements of the device under test.

      This tester logic is a simple but powerful RISC processor based
on a Load/Store architecture as shown in Fig. 1.  The ALU contains 3
functional units and multiple data paths optimized for tester
operation.  Operands are provided by a dual port Register File and
the DUT input.  Results can be stored back to the Register File
and/or can be put to the DUT interface.

      Tester operation is controlled by a Long Instruction Word (LIW)
provided by the Control Store to the Sequencer unit of the tester.
An
 LIW contains opcodes for the functional units and specifies data
paths and instructions for the control unit.  Control flow in the
tester is completely separated from data paths.  The Sequencer
determines the instruction sequence depending on the tester status
(e.g., branches,  condition codes, event counter, errors) and
Sequencer instructions. In  addition, a part of the LIW is used to
set or check control signals explicitly on a cycle by cycle base.
All operations are completed in one cycle to match memory card
bandwidth.

Fig. 2 Tester Operating Modes:
  a) Load/Read Tester Control Store/Register File
  b) Inter...