Browse Prior Art Database

Improving L1/L2 Cast-Out Performance in an Inclusive Serial Cache

IP.com Disclosure Number: IPCOM000118272D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Venkatramani, J: AUTHOR

Abstract

Disclosed is a multi-level cache hierarchy that maintains an inclusion property, i.e., a lower level cache always includes the higher level cache. Therefore, there is a potential for multiple levels to have the same cache block valid. In these situations, if the lower level cache has dirty data that is marked "Inclusive", the higher level cache may or may not have dirty data. In case a), the higher level cache has dirty data; its data is "dirtiest" and is the correct data that is to be written back to main memory. In case b), the higher level cache has no dirty data; the lower level cache has the correct data that needs to be written back to main memory. The lower level cache has to "snoop" the higher level cache and wait for the snoop response to distinguish between these two cases.

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Improving L1/L2 Cast-Out Performance in an Inclusive Serial Cache

      Disclosed is a multi-level cache hierarchy that maintains an
inclusion property, i.e., a lower level cache always includes the
higher level cache.  Therefore, there is a potential for multiple
levels to have the same cache block valid.  In these situations, if
the lower level cache has dirty data that is marked "Inclusive", the
higher level cache may or may not have dirty data.  In case a), the
higher level cache has dirty data; its data is "dirtiest" and is the
correct data that is to be written back to main memory.  In case b),
the higher level cache has no dirty data; the lower level cache has
the correct data that needs to be written back to main memory.  The
lower level cache has to "snoop" the higher level cache and wait for
the snoop response to distinguish between these two cases.  The lower
level cache begins the access to its data storage after this snoop
response.  This increases the latency for cast-outs.

      This invention proposes a technique to reduce this
latency.  The lower level cache starts accessing its own storage
simultaneously with the snoop to the higher level cache.  Since the
snoop response for case a) is a retry (or backoff) in most coherence
protocols, the retry automatically "kills" the speculative access
that the lower level cache has started.  The snoop response for case
a) is a "null" or no response and this allows the speculative
cast-out to complete...