Browse Prior Art Database

Method for Power Management of a Cardbus PC Card

IP.com Disclosure Number: IPCOM000118278D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

LaBerge, PA: AUTHOR [+3]

Abstract

Disclosed is a power management technique which allows a CardBus PC card to initially power-up in a limited function "low power" state and remain in that mode until the host system gives it permission to draw the additional supply current required to become fully operational. It allows a CardBus PC card to meet the stringent PC Card Standard requirement that a maximum of only 70 milliamps of supply current be drawn from the 3.3 volt power supply during the period immediately following power-up.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Method for Power Management of a Cardbus PC Card

      Disclosed is a power management technique which allows a
CardBus PC card to initially power-up in a limited function "low
power" state and remain in that mode until the host system gives it
permission to draw the additional supply current required to become
fully operational.  It allows a CardBus PC card to meet the stringent
PC Card Standard requirement that a maximum of only 70 milliamps of
supply current be drawn from the 3.3 volt power supply during the
period immediately following power-up.

      The power management technique is based upon a "Power Control
Register" implemented within a CardBus PC card's hardware.  The
register is read/write accessible from the CardBus system's main
processor through Input/Output (I/O) or memory space.  Each bit
within the register directly controls the "power state" of a specific
portion of the circuitry contained on the PC card.  When inactive,
the bit forces the associated circuitry into a non-functioning "low
power" mode.  When active, the bit forces the associated circuitry
into a normal operational mode.

      The bits in the Power Control Register are set to their default
state of "inactive" by the reset signal which is activated on the
CardBus when the host system is powered-up.  This initially places
all the circuitry controlled by the register in the "low power" mode,
thereby minimizing the PC Card's overall power consumption.  After
the host system has completed its power-up initialization and
configuration tasks, it will activate device driver software which is
unique to the specific CardBus PC card.  The device driver software
will write the Power Control Register to activate, or "power-up", the
circuitry on the PC card required to perform the intended function.

      A portion of the PC card's circuitry is excluded from control
of the Power Control Register.  The CardBus specification requires
that a PC Card always be able to respond to reads and writes to its
configuration registers and to reads of its Card Information
Structure (CIS) data.  The circuitry which implements these functions
is always activated and is not affected by any of the bits in the
Power Control Register.

      The Figure illustrates the system environment of the Power
Control Register concept.  Each of the Power Control Register bits
are routed as signals to a specific portion of the PC card's
circuitry.  When deactivated the signal forces its associated
circuitry into a "low power" mode through various techniques such as:
  1.  deactivating or reducing the frequency of the circuitry's
       clocks;
  2.  forcing the circuitry into "reset mode"; or
  3.  disabling the voltage regulation device that supplies
       power to the circuitry.

      The following sequence of events illustrates how the Power
Control Register is used in a system environment:
  1. ...