Browse Prior Art Database

Processor Single Step Trace Facility Enhancements

IP.com Disclosure Number: IPCOM000118286D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Levine, FE: AUTHOR [+2]

Abstract

Providing instruction and address traces is a very important part of system tuning and future system design. There are many different methodologies for providing this support, each of which has its benefits and problems. Disclosed is a reasonably cost-effective approach that speeds the ability to produce processor traces.

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Processor Single Step Trace Facility Enhancements

      Providing instruction and address traces is a very important
part of system tuning and future system design.  There are many
different methodologies for providing this support, each of which has
its benefits and problems.  Disclosed is a reasonably cost-effective
approach that speeds the ability to produce processor traces.

      The PowerPC* architecture provides for an optional trace
facility.  By setting a specific bit in the Machine Status Register
(MSR), the processor enters the single step mode.  In the single step
mode, after an instruction is executed, a single step interrupt is
taken.  The information provided by the hardware at the time the
single step interrupt is taken may be used to create instruction
traces.

The instruction/data tracing algorithm is enhanced via two methods:
  o  First, more instruction decoding information is available
      at the time the interrupt is taken.
  o  Second, instead of collecting trace data in a processor/memory
      buffer, the processor or the interrupt routine directly writes
      the data at a specified memory address, which could be defined
      in Input/Output (I/O) space.  Data written to a specific
      address is written to the system bus.  The data written to
      the specified address on the system bus is collected via a
      device attached to the system bus for future processing.

      Providing the instruction decoding information directly in the
hardware avoids the need for real time instruction decoding in the
software and allows the software to quickly determine the information
that needs to be written to the system bus.  For example, the
following information, returned in SRR1, could be used to further
decode the instruction by the hardware:
  Bit Number Description
  33 {1}     Set to 1 if the traced instruction is icbi; otherwise
              set to 0.
  34 {2}     Set to 1 if the traced instruction is dcbt, dcbtst,
              dcbz, dcbst, dcbf, or dcbi; otherwise set to 0.
  35 {3}     Set to 1 if the traced instruction is a Load
              instruction or eciwx; may be set to...