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Browse Prior Art Database

Technique to Support Multiple L2 Cache Controller Interfaces

IP.com Disclosure Number: IPCOM000118298D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Capps, LB: AUTHOR [+2]

Abstract

Many low cost Peripheral Component Interconnect Bridge and Memory Controller (PCIB/MC) chips have an on-chip level-2 (L2) cache controller. With external SRAM and TAG_RAM chips, the on-chip L2 cache controller provides a complete L2 cache solution.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Technique to Support Multiple L2 Cache Controller Interfaces

      Many low cost Peripheral Component Interconnect Bridge and
Memory Controller (PCIB/MC) chips have an on-chip level-2 (L2) cache
controller.  With external SRAM and TAG_RAM chips, the on-chip L2
cache controller provides a complete L2 cache solution.

      Another way to provide a complete L2 cache is to use an
external stand-alone L2 controller with integrated fast SRAM.  This
solution offers higher performance.

      This invention disclosure describes a single L2 interface which
supports both the on-chip L2 cache controller with external
SRAM/TAG_RAM and the external stand-alone L2 controller with
integrated fast SRAM.  This invention minimizes the number of L2
connector pins and also  accommodates a full range of L2 cache
solutions from low performance/low  price to high performance.
Between the two types of L2 interface, some  signals have a common
definition while other signals are exclusive. The  block diagram
below depicts an overview of the L2 cache system and associated
subsystems.
  +-------------------+              +----------------+
  |  L2 Cache Module  |              |   Processor    |
  |  (Memory only or  |              |    (CPU)       |
  |   Full L2)        |              |                |
  +-------------------+              +----------------+
       |      |                                 |
       |      |   Addr/Data/Arbitration/Ctrl    |
       |      +---------------------------------+
       |      |                                 |
       |      |                                 |
       |      |                     +----------------+
       |      | SRAM & TAG Control  |                |  Memory Bus
       |      +---------------------|  PCIB/MC Chip  |------------
       |                            |                |
       |                            +----------------+
  L2 Control & Module ID                   |
                                           |
                                           |
                                        PCI Bus

      L2 cache is implemented in the form of a module.  The module
interface supports either a full L2 module (L2 controller and L2 RAM)
or an L2 memory only module (L2 RAM).  Three types of signals exist
in this interface:
  1.  Common - signals needed for both L2 module types.
  2.  Exclusive - signals needed by...