Browse Prior Art Database

Channel Packaging Verification for Complex Channel Subsystems

IP.com Disclosure Number: IPCOM000118299D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 129K

Publishing Venue

IBM

Related People

Halma, MJ: AUTHOR [+3]

Abstract

Disclosed is a program implementation using small data objects and a small amount of accompanying code to perform a complex task. The novelty of this implementation is in the content and flexibility of data objects and the varied use made of those data objects.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Channel Packaging Verification for Complex Channel Subsystems

      Disclosed is a program implementation using small data objects
and a small amount of accompanying code to perform a complex task.
The novelty of this implementation is in the content and flexibility
of data objects and the varied use made of those data objects.

      Although this approach could be applied to any similar problem,
this paper will deal with our solution to providing channel packaging
checking for S/390 processors.  The initial task is to segment the
problem into smaller pieces.  These smaller pieces may relate to the
physical properties of the channel subsystem or be more logical in
nature.

      The result is three categories of data objects that we call
Rule Tables.  Each Rule Table contains information on the target
CHPIDs to be altered, the data to alter, and unique iteration and
count information.  The program contains a set of Rule Tables for
each channel hardware type supported by each processor type.  For
example, this results in a set of Rule Tables for ESCON channels on
an ES/9000 9021 processor.  A different set of Rule Tables exist for
ESCON channels on an ES/9000 9672 processor.  The same is true for
parallel channels and so forth.

      Different code paths use the Rule Tables to accomplish
different tasks.  In one application, the Rule Tables are used to
initialize an array such that each element of the array corresponds
to a CHPID number and the contents of the element indicates all the
valid channel types for the associated location.  For the predominant
use of the Rule Tables, the program is provided a corresponding array
with an indication of what channel type the user defined for each
CHPID.  In this application, the Rule Tables for each defined CHPID
are applied to the valid channel types, which may limit the valid
types for other CHPID numbers.  When a defined CHPID is found to be
not valid, the program indicates the discrepancy and reason in the
array.  The modified array is returned to the calling program.

      In yet another use of the Rule Tables, a different application
creates a script document that reports all the rules enforced by the
checking program.  This document is then used for
design/implementation review, as well as for customer documentation.

      To demonstrate the use of a Rule Table, refer to the
Figure.  The Slot Rule is the smallest granularity of checking in our
implementation and is used to ensure common channel types are defined
in contiguous locations.  As an example, the parallel channel card
for an R3 model 9672 provides 3 interfaces (CHPIDs), but each slot
for a channel card on an R3 allows for 4 CHPIDs.  This forces us to
have two rules for parallel.  The first ensures that a mix of
parallel and another channel type does not occur and the second
prevents any type from  being defined in the fourth available CHPID.

      To illustrate the logic used to act o...