Browse Prior Art Database

Single-Pass Counting of Floating Point Operations in a Processing System

IP.com Disclosure Number: IPCOM000118304D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Levine, FE: AUTHOR [+2]

Abstract

There is no "approved industry standard that defines a floating point operation." That is, the definition of a floating point operation is in the eyes of the beholder. Typically, however, there is some interest in comparing the perceived performance of a machine by characterizing its performance in terms of megaflops per second, or a million floating point operations per second.

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Single-Pass Counting of Floating Point Operations in a Processing
System

      There is no "approved industry standard that defines a floating
point operation."  That is, the definition of a floating point
operation is in the eyes of the beholder.  Typically, however, there
is some interest in comparing the perceived performance of a machine
by characterizing its performance in terms of megaflops per second,
or a million floating point operations per second.  There are,
however, some  operations that are typically counted differently, for
example, how many  floating point operations is a divide, square
root, or sin function? What about a machine that does an add and a
multiply in a single cycle,  which is typically counted as two
floating point operations?  Because the Cray computer was one of the
first to provide high speed floating point performance, one common
practice is to normalize the number of floating point operations to
what is typically done on a Cray.  Even this approach has some
drawbacks in that there are different versions of Cray computers that
perform some functions in a different number of  cycles.  In addition
to the problem of how to count operations, there is a strong desire
by the end user to only have to count the operations  once.  This is
especially true on some of the long running jobs that can  last weeks
or even months.

      The PowerPCTM Performance Monitor is a software-accessible
mechanism intended to provide detailed information concerning the
utilization of PowerPC* instruction execution and storage control.
The monitor consists of an implementation-dependent number (2-8)
32-bit counters (PMC1, PMC2, PMC3, ..., PMC8) to be used to count
Processor/Storage performance related events.

      The Monitor Mode Control Register (MMCR0) establishes the
function of the counters.  The counters and the MMCR0 physically
reside on the 6XX chip and are addressable for read or write via
mfspr or mtspr  instructions.  Writing to these SPRs is only allowed
in privileged state.  Reading from these SPRs may also be allowed in
the problem state.  Reading these counters/registers does not change
their content.

      The Monitor Mode Control Register (MMCR0) is partitioned int...