Browse Prior Art Database

Technique for Handling Multiple Bank Dynamic Random Access Memory Dual Inline Memory Modules

IP.com Disclosure Number: IPCOM000118305D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Capps, LB: AUTHOR [+3]

Abstract

Industry standard 168-pin Dynamic Random Access Memory (DRAM) Dual Inline Memory Module (DIMMs) are usually the single bank type. That means that it requires only one Row Address Strobe (RAS) control signal to handle the row address strobing of the row address onto the DIMM module.

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This is the abbreviated version, containing approximately 64% of the total text.

Technique for Handling Multiple Bank Dynamic Random Access Memory
Dual Inline Memory Modules

      Industry standard 168-pin Dynamic Random Access Memory (DRAM)
Dual Inline Memory Module (DIMMs) are usually the single bank type.
That means that it requires only one Row Address Strobe (RAS) control
signal to handle the row address strobing of the row address onto the
DIMM module.

      DRAM memory DIMM vendors are often requested to offer the dual
bank type DIMMs so that systems developers can take advantage of the
significant lower price of older memory technology, for example 4
M-bit DRAM chips.  The dual bank DRAM memory DIMM requires two RAS
control signals to handle the row address strobing of the address
onto the DIMMs.  One RAS control signal selects the row address
strobe of one memory bank and the other RAS control signal selects
the other row address strobe of the second memory bank.

      The disclosed invention describes a scheme to handle multiple
bank DRAM memory DIMMs.

      Many low-cost memory controllers used in workstations support
up to eight RAS control signals (RAS1..RAS8) or eight memory bank
select control signals.  Some workstations support only six memory
slots due to physical limitations.  Each slot can accommodate one
DRAM memory DIMM.

      If a workstation was designed to support only single bank DRAM
memory DIMMs, then one RAS control signal would be used for each
memory DIMM slot.  For example, memory DIMM slot. ...