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Mechanism for Accessing a Floating-Point Status and Control Register with Minimal Performance Impact

IP.com Disclosure Number: IPCOM000118308D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Burgess, B: AUTHOR [+4]

Abstract

Microprocessors having Floating-Point Units (FPUs) complying with the "Institute of Electrical and Electronics Engineers Standard for Binary Floating-Point Arithmetic" (IEEE-754) have a status and control register (FPSCR) that both indicates result status of the previously executed instruction or instructions and determines the method of operation when executing said instructions: status bits indicate result status and control bits determine method of operation. Instructions are provided for moving data from the FPSCR to a Floating-Point Register (FPR) for the purpose of "reading" said status bits and other instructions are provided for moving data to the FPSCR from an FPR for the purpose of setting the control bits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Mechanism for Accessing a Floating-Point Status and Control Register
with Minimal Performance Impact

      Microprocessors having Floating-Point Units (FPUs) complying
with the "Institute of Electrical and Electronics Engineers Standard
for Binary Floating-Point Arithmetic" (IEEE-754) have a status and
control register (FPSCR) that both indicates result status of the
previously executed instruction or instructions and determines the
method of operation when executing said instructions:  status bits
indicate result status and control bits determine method of
operation.  Instructions are provided for moving data from the FPSCR
to a Floating-Point Register (FPR) for the purpose of "reading" said
status bits and other instructions are provided for moving data to
the FPSCR from an FPR for the purpose of setting the control bits.
Said instructions are here referred to as mffpscr (move from FPSCR)
and mtfpscr (move to FPSCR), although the actual instructions may
have different names.

      Superscalar microprocessors having said instructions, sometimes
find it necessary to serialize said instructions; if a mtfpscr
instruction is dispatched to the FPU, no other subsequent instruction
would be dispatched until the mtfpscr instruction is completed,
thereby ensuring that any subsequent floating-point instruction would
be operating according to the FPSCR control bits just "set" by the
mtfpscr instruction.  Likewise, dispatch of a mffpscr instruction is
stalled until all sub...