Browse Prior Art Database

Instruction Match Function for Processor Performance Monitoring

IP.com Disclosure Number: IPCOM000118313D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Levine, FE: AUTHOR [+3]

Abstract

Disclosed is a method in a processor system that provides a User Interface that allows for the counting of user selectable specific instruction, the number of dispatches of the selected instruction, the number completed, and the length of time of execution of the specific instruction.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

Instruction Match Function for Processor Performance Monitoring

      Disclosed is a method in a processor system that provides a
User Interface that allows for the counting of user selectable
specific instruction, the number of dispatches of the selected
instruction, the number completed, and the length of time of
execution of the specific instruction.

      The method entails the implementation of one or more
Instruction Match Registers (IMRs).  An IMR allows the specification
of a specific instruction or set of instructions, which can be used
during a processor's execution path to count performance information
related to the instructions that match the specification.

      In a typical embodiment, an IMR would contain a field for the
instruction opcode, any opcode extension, and a mask field for
requiring a match on the specific field or bits within the field.

      In an alternative embodiment, an IMR may contain simply a set
of internal opcodes representing sets of predetermined instructions
types.

      Typically, the dispatch unit of the processor would identify
the instruction and tag it for subsequent measurement data.
Individual processor units provide relevant information to the
performance monitor  subcomponent of the processor, which records
relevant information in in counters.

      In order to determine future processor architecture
enhancements or to eliminate complex instructions that do not give
enough "bang for the buck," there is often a need to understand the
number of occurrences of a specific instruction.  For example, the
lscbx is an example of an instruction that was supported in the Power
architecture, but not the PowerPC processor architecture.  By
providing a means to directly count the number of occurrences of the
instruction and the length of time relative to other instructions,
one can determine the benefit of adding that instruction back into
the architecture or a set of candidate replacement instructions.

      One other problem that can be solved by the introduction of the
capability of identifying an instruction to match or count matches
for a specified instruction is the ability to provide software work
arounds related to processor problems (sometimes found in very early
versions of  processors).  The approach is to cause a performance
monitoring interrupt  when the instruction is dispatched or completed
and then detect and, if  necessary, fix the problem.

      The PowerPCTM Performance Monitor is a software accessible
mechanism intended to provide detailed information concerning the
utilization of PowerPC* instruction execution and storage control.
The monitor consists of an implementation dependent number (2-8)
32-bit counters (PMC1, PMC2, PMC3, ..., PMC8) to be used to count
Processor/Storage performance related events.

      The Monitor Mode Control Register (MMCR0) establishes the
function of the counters.  The counters and the MMCR0 physically
res...