Browse Prior Art Database

Highly Parallel, Flexible Half Pel and Dual Prime Motion Estimation System

IP.com Disclosure Number: IPCOM000118324D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 6 page(s) / 239K

Publishing Venue

IBM

Related People

Butter, AS: AUTHOR [+2]

Abstract

Disclosed is a scalable algorithm which supports both half pel and dual prime motion estimation. An overview of the disclosed system is provided in Fig. 1, comprising a Pixel Interpolation Pipeline, shift registers and three sets of motion estimation processors operating in a parallel and pipelined manner to meet the stringent requirements of real time video compression.

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Highly Parallel, Flexible Half Pel and Dual Prime Motion Estimation
System

      Disclosed is a scalable algorithm which supports both half pel
and dual prime motion estimation.  An overview of the disclosed
system is provided in Fig. 1, comprising a Pixel Interpolation
Pipeline, shift  registers and three sets of motion estimation
processors operating in a  parallel and pipelined manner to meet the
stringent requirements of real  time video compression.

      One of the key elements of the invention is the Pixel
Interpolation Pipeline, which is shown in additional detail in Fig.
2.  The component takes in full pel reference pixel data and outputs
the original full pel and three interpolated (averaged) reference
pixels in a synchronous manner.  This reference data can either be
dual prime or  non-dual prime data depending on whether dual prime or
half pel motion  estimation, respectively, is being performed.  The
reference data will  typically originate from either an on-chip or
off-chip memory element.  When valid reference data is input to the
Pixel Interpolation  Pipeline, it will pass through a series of
latching stages.  The number  of stages required is inversely
proportional to the number of valid pixels input per clock cycle.  In
order to perform all the desired motion  estimation searches per
pixel line, the following formula is used to determine the number of
latching stages: #_of_stages = 21//#_of_vld_pels

      In this formula, #_of_vld_pels is the number of valid pixels
input per clock cycle and #_of_stages is the number of sequential
latching stages required to hold the pixel data inside the pipeline.
The constant factor of 21 represents the addition of 18 pixels per
line used  to generate all half pel and dual prime macroblock search
locations for  the motion estimation algorithms, plus 3 pixels from a
second line which are required to generate the first four
synchronously output results.  The number of stages requirement stems
from the need to have  both current macroblock line pixel data, as
well as subsequent macroblock  line pixel data in order to generate
both vertically and diagonally half  (four-way) interpolated
reference macroblocks.  The // operation denotes  integer division
with rounding away from zero.  For purposes of this disclosure, the
preferred embodiment sets the number of valid pixels input per clock
cycle at 2, requiring an eleven stage pipeline.

Operation of the Pixel Interpolation Pipeline proceeds as follows:

      As the first line of valid pixels are received by the pipeline,
two synchronized pixel types (full and horizontal half pel) are
output.  Full pel values are equal to the valid pixel data input to
the pipeline, while horizontal half pel values are equal to the
interpolation (average) of the corresponding synchronously output
full pel value with the next full pel value of the same pixel line.

      As the second and subsequent lines of valid pix...