Browse Prior Art Database

Low-Capacitance Thin Film Transistor

IP.com Disclosure Number: IPCOM000118327D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Wright, SL: AUTHOR

Abstract

Disclosed is a Thin Film Transistor (TFT) device which has low parasitic capacitance. This parasitic capacitance is a strong limiting factor in the design of high resolution Active-Matrix Liquid-Crystal Displays (AMLCDs). The low capacitance is achieved by removing unnecessary portions of the gate metal layer, forming a gate in the shape of a cross. As compared to I-shaped TFTs, the parasitic capacitance is reduced by about 40%.

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Low-Capacitance Thin Film Transistor

      Disclosed is a Thin Film Transistor (TFT) device which has low
parasitic capacitance.  This parasitic capacitance is a strong
limiting factor in the design of high resolution Active-Matrix
Liquid-Crystal Displays (AMLCDs).  The low capacitance is achieved by
removing unnecessary portions of the gate metal layer, forming a gate
in the shape of a cross.  As compared to I-shaped TFTs, the parasitic
capacitance is reduced by about 40%.

      Amorphous Si TFTs are used in AMLCDs because they provide
adequate drive current and very low off current.  They can be
inexpensively fabricated with high yield on glass substrates.
However, the pixel capacitance can be quite small (less than 50 fF),
and this places a constraint on the allowable parasitic capacitances
in the array.  TFTs have a parasitic capacitance due to stored charge
in the channel and due to overlap of source/drain and gate metals.
This capacitance causes undesirable voltage feedthru to the pixel
electrode in AMLCDs, a problem which becomes more severe as display
resolution is  increased.  In particular, the TFT gate to source
capacitance causes a  fraction of the applied gate voltage to
feedthru to the pixel each time  the gate voltage is changed.  This
voltage change, and variations in this  voltage change with time and
location on the array, cause undesirable effects in the pixel
charging and discharging process.  For a given pixel  size and liquid
crystal cell, there are several approaches to alleviate  this
problem.  First, a storage capacitor is added to the cell,
increasing the total load capacitance driven by the TFT.  This
approach decreases the voltage feedthru but requires increased TFT
drive current  and increased opaque metal area to create the storage
capacitor, decreasing the aperture ratio.  This performance tradeoff
is evident in  present AMLCD designs.  A second approach involves
multi-level drive signals, in which the gate voltage feedthru is
compensated by applying a  voltage pulse to the adjacent gate line.
Compensation schemes such as this significantly increase drive
electronics cost and complexity. A  third approach is to minimize the
parasitic capacitance in the TFT itself.  If this can be done, the
constraints on the size of the storage capacitor will be dominated by
crosstalk and not by voltage feedthru.  Present inverted-staggered,
bottom-gate TFT configurations do not result in low channel
capacitance.  Approaches toward reducing parasitic capacitance (and
channel length) include back-etched channel  TFTs and self-aligned
TFTs.  Self-aligned approaches involve process innovation such as
ion-shower doping, back-side exposure, or selective  deposition.  All
of these methods involve increased risk and cost.

      Inverted-staggered TFT designs have an opaque gate layer
beneath the device, thereby blocking the light coming through this
portion of the substrate which would otherw...