Browse Prior Art Database

Effective Cache Mechanism for Texture Mapping

IP.com Disclosure Number: IPCOM000118346D
Original Publication Date: 1996-Dec-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 6 page(s) / 159K

Publishing Venue

IBM

Related People

Kawase, K: AUTHOR

Abstract

Disclosed is an effective cache mechanism for texture mapping, which is one of the most important facilities in 3D graphics systems. Current high-end 3D graphics system hardware for texture mapping is very expensive because such systems must provide duplicate texture images in order to reduce the access time of the texture memory. Fig. 1 shows an example of a current high-end 3D graphics system.

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Effective Cache Mechanism for Texture Mapping

      Disclosed is an effective cache mechanism for texture mapping,
which is one of the most important facilities in 3D graphics
systems.  Current high-end 3D graphics system hardware for texture
mapping is very expensive because such systems must provide duplicate
texture images in order to reduce the access time of the texture
memory.  Fig. 1 shows an example of a current high-end 3D graphics
system.

      The Raster Command Processor broadcasts projected triangles
on the Triangle Bus to the eight Fragment Generators.  Each Fragment
Generator is responsible for the rasterization of 1/8 of the pixels
in the frame-buffer, with the pixel assignments finely interleaved to
ensure that even small triangles are partially rasterized by each of
the Fragment Generators.  Each Fragment Generator computes the
intersection of the set of pixels covered by the triangle and
generates a fragment for each of these pixels.  Color, depth, and
texture coordinates are assigned to each fragment on the basis of the
initial and slope values.  Each Fragment Generator has a local copy
of the texture memory, which it looks up by using the texture
coordinates.  Since each Fragment Generator has its own copy of the
texture memory, the total texture memory required is eight times
larger.  For example, if a user requires 16 MB for storing texture
images, the system must provide 128 MB of texture memory.  This
drastically increases the system cost.

      The disclosed system introduces a texture cache mechanism that
holds a partial copy of the texture memory to avoid having to store a
copy of the entire texture memory.  Figs. 2 and 3 show overviews of
the disclosed system.

      The system has eight Fragment Generators, with an additional
Texture Cache Manager.  The Raster Command Processor broadcasts a
projected triangle to the Texture Cache Manager, as well as the
Fragment Generators, with a unique sequence ID.  Each Fragment
Generator has an  input FIFO to buffer the latency of the texture
cache fill.

      The Texture Cache Manager provides a cache tag to manage the
cache contents.  Each entry of the cache tag holds a texture memory
address, a cache block number, and a reference count.

      Each Fragment Generator has a cache data, as well as a cache
tag.  The cache tag is different from that of the Texture Cache
Manager and holds only a texture memory address and a cache block
number.

      Fig. 4 shows how a texture memory address (24-bit) is
translated from two-dimensional texture coordinates i and j (10 bits
each).  The texture base is a pointer of the texture image in texture
memory space.  The texture memory address is divided into an 18
bit-block number and a 6-bit offset.  Each block consists an 8 x 8
rectangular region o...