Browse Prior Art Database

Method for Improving Peripheral Component Interconnect Bus Bandwidth for Systems with Limited Prefetch

IP.com Disclosure Number: IPCOM000118368D
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Schlude, TJ: AUTHOR [+2]

Abstract

Disclosed is a method for improving Peripheral Component Interconnect (PCI) bus bandwidth for an adapter card in a system where the memory controller cannot prefetch data. The target device disables address decoding for a particular region and becomes an address funnel.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Improving Peripheral Component Interconnect Bus Bandwidth
for Systems with Limited Prefetch

      Disclosed is a method for improving Peripheral Component
Interconnect (PCI) bus bandwidth for an adapter card in a system
where the memory controller cannot prefetch data.  The target device
disables address decoding for a particular region and becomes an
address funnel.

      A 32 bit wide, 33 MHz PCI bus can stream its data during a
burst transfer, which significantly increases the data throughput.  A
PCI burst transaction can be generally described as:
  o  master requests the bus
  o  arbitrator grants the bus when available
  o  address phase
  o  data phase

During the data phase, four bytes of data are transferred on every
clock cycle until the master runs out of data, the target terminates
the transaction, or the latency timer has expired.  This results in a
peak data transfer rate of 4 bytes x 33 MHz which equals 132
MegaBytes/second (MB/s).  See Fig. 1.

      The memory controller/PCI bridge for the reference platform is
only capable of sustaining a burst of 32 bytes at a time from system
memory.  Because of this limitation, the master has to constantly
re-arbitrate during a long transfer.  This reduces the peak data
transfer rate to approximately 96 MB/s (32 bytes x 33 MHz / (1 bus
request + 1 bus grant + 1 address phase + 8 data phases)).  See Fig.
2.

      A further bottleneck resides on the adapter in the form of a
generic PCI interface chip from Applied Micro Circuits Corporation,
the AMCC S5933.  Because the adapter is memory-mapped, every address
that is passed across the PCI bus goes...