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Conditional Branch Handling in an Emulation System Using Dynamic Instruction Translation

IP.com Disclosure Number: IPCOM000118369D
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 246K

Publishing Venue

IBM

Related People

Scalzi, CA: AUTHOR [+2]

Abstract

A method of locating existing target machine instruction translations of source machine instructions in a system emulating a source processor in a different target processor by means of dynamic translation of source processor instructions to target processor equivalents and saving them for reuse was described in (*). The instruction translations of the source processor instructions are found by having them mapped by a very large target virtual area called the Instruction Translation Map (ITM). There is one entry in the map for each possible source instruction, and it indicates whether or not an instruction translation exists for the source instruction represented by the entry and, if there is one, its virtual address in another large target virtual area called the Instruction Translation Region (ITR).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 23% of the total text.

Conditional Branch Handling in an Emulation System Using Dynamic
Instruction Translation

      A method of locating existing target machine instruction
translations of source machine instructions in a system emulating a
source processor in a different target processor by means of dynamic
translation of source processor instructions to target processor
equivalents and saving them for reuse was described in (*).  The
instruction translations of the source processor instructions are
found by having them mapped by a very large target virtual area
called the Instruction Translation Map (ITM).  There is one entry in
the map for each possible source instruction, and it indicates
whether or not an instruction translation exists for the source
instruction represented by  the entry and, if there is one, its
virtual address in another large target virtual area called the
Instruction Translation Region (ITR). The  translations are performed
as the source instructions are encountered in  the emulated execution
of the source program.  These are stored for execution, and possible
future reuse, in the very large target virtual  area called the ITR,
which holds all target machine instruction translations of all source
machine instructions actually executed by a  program.

      The ITR is organized in sections, each of which will hold the
translations of an associated source program storage section.  There
is a direct addressing relationship between a source section and the
target ITR section in which will be stored the instruction
translations of the source instructions in the source section.  Given
the address of  a source section, the address of the ITR section to
hold its translations  can be directly calculated.  The size of an
ITR section should be chosen such that it is certain that any
possible normally anticipated translation of any source section will
fit in the virtual area reserved.  Since the virtual storage area
reserved will only be backed  by real storage as required by the
creation of actual translations, the  assignment of a very large
virtual storage area reserved to hold all the  ITR sections is not
wasteful of storage.  The large virtual area is assigned such that,
given a source section address, the corresponding ITR target virtual
address can be directly calculated.  Storing an instruction
translation of a source instruction of the section can be very
efficient since the ITR section to contain the target instructions
which are to perform the function of the source instruction can be
directly addressed.  Each ITR section contains a header part at a
fixed relative place in the section.  The header contains descriptive
information about the translations stored in the ITR section and
storage allocation information required to manage the placement of
new translations into the section.  Translation of source
instructions to target instructions occurs as the source instructions
are encountered in source machine p...