Processor Performance Monitoring with Depiction of the Efficiency of Bus Utilization and Memory Accesses of Superscalar Microprocessor
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Levine, FE: AUTHOR [+2]
Disclosed is a method that expands on the support defined in the PowerPC* 604 RISC Microprocessor User's Manual that provides to the software a representation of the efficiency of the bus utilization and its memory accesses. Enough information is provided to facilitate processor, system and compiler/coding performance improvements.
Processor Performance Monitoring with Depiction of the
of Bus Utilization and Memory Accesses of Superscalar Microprocessor
a method that expands on the support defined in
the PowerPC* 604 RISC Microprocessor User's Manual that provides to
the software a representation of the efficiency of the bus
utilization and its memory accesses. Enough information is provided
to facilitate processor, system and compiler/coding performance
approach analyzes whether the bus unit has enough
capacity to feed the microprocessor or whether the bus unit is too
large and some area savings can be gained by reducing its
6XX Performance Monitor is a software accessible
mechanism intended to provide detailed information concerning the
utilization of PowerPC instruction execution and storage control.
The monitor consists of an implementation dependent number (2-8)
32-bit counters (PMC0, PMC1..., PMC7) to be used to count
Processor/Storage performance related events.
Mode Control Registers (MMCR0, MMCR1) establish the
function of the counters. The counters and the MMCRn physically
reside on the 6XX chip and are addressable for read or write via
mfspr or mtspr instructions. Writing to these SPRs is only allowed
in supervisor or privileged state. Reading from these SPRs may also
be allowed in the problem state. Reading these counters/registers
does not change their content.
Mode Control Registers (MMCRn) are partitioned into
bit fields that allow for selection of events (signals) to be
recorded (counted). Selection of allowable combinations of events,
causes the counters to operate concurrently. The MMCRn includes
controls, such as, counter enable control, counter negative
interrupt control, counter event selection, and counter freeze
6XX chips which support Performance Monitoring
contains an implementation dependent number of events that can be
selected for counting.
performance monitor facility is enabled for counting,
the processor may support some additional shadow registers to
facilitate sampling, that is, SPRs which are periodically updated.
One of these registers is called the Sampled Instruction Address
Register (SIAR), which is the effective address an instruction being
"sampled," that is, the sampled instruction. Another shadow
register is called the Sampled Data Address Register (SDAR), which
should contain the effective address of the operand of the SIAR,
hardware to count the following events, one could
gain enough knowledge about the bus unit's behavior in order to be
able to make a decision about changing the software or hardware:
1. Number of icache lines filled
2. Number of dcache lines filled
3. Number of snoops
4. Number of cycles no data bus transactions...