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Processor Performance Monitoring with a Depiction of the Efficiency of the Cache Coherency Protocol of a Superscalar Microprocessor in an Symmetric Multiple Processor Environment

IP.com Disclosure Number: IPCOM000118373D
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 150K

Publishing Venue

IBM

Related People

Levine, FE: AUTHOR [+2]

Abstract

Disclosed is a method that expands on the support defined in the PowerPC* 604 Reduced Instruction Set Computer/Cycles (RISC) Microprocessor User's Manual. The disclosed method provides to the software a representation of the efficiency of the cache coherency protocol as it occurs during the execution of software.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Processor Performance Monitoring with a Depiction of the Efficiency
of the Cache Coherency Protocol of a Superscalar Microprocessor in
an Symmetric Multiple Processor Environment

      Disclosed is a method that expands on the support defined
in the PowerPC* 604 Reduced Instruction Set Computer/Cycles (RISC)
Microprocessor User's Manual.  The disclosed method provides to the
software a representation of the efficiency of the cache coherency
protocol as it occurs during the execution of software.

      The method provides for statistical information to be used to
determine the efficiency of the cache coherency protocol in an SMP
system.  The information provides for processor, system and
compiler/coding performance improvements.

      The PowerPC Performance Monitor is a software accessible
mechanism intended to provide detailed information concerning the
utilization of PowerPC instruction execution and storage control.
The monitor consists of an implementation dependent number (2-8)
32-bit counters (PMC1, PMC2, ..., PMC8) to be used to count
Processor/Storage performance related events.

      The Monitor Mode Control Registers (MMCR0, MMCR1) establish the
function of the counters.  The counters and the MMCRn physically
reside on the processor and are addressable for read or write via
mfspr or mtspr  instructions.  Writing to these SPRs is only allowed
in supervisor or privileged state.  Reading from these SPRs may also
be allowed in the problem state.  Reading these counters/registers
does not change their  content.

      The Monitor Mode Control Registers (MMCRn) are partitioned into
bit fields that allow for selection of events (signals) to be
recorded (counted).  Selection of allowable combinations of events
causes the counters to operate concurrently.  The MMCRn includes
controls, such as,  counter enable control, counter negative
interrupt control, counter event  selection, and counter freeze
control.

      The PowerPC processors which support Performance Monitoring
contains an implementation dependent number of events that can be
selected for counting.

      While the performance monitor facility is enabled for counting,
the processor may support some additional shadow registers to
facilitate sampling, that is, SPRs which are periodically updated.
One of these registers is called the Sampled Instruction Address
Register (SIAR), which is the effective address an instruction being
"sampled," that is,  the sampled instruction.  Another shadow
register is called the Sampled  Data Address Register (SDAR), which
should contain the effective address  of the operand of the SIAR,
when applicable.

      One way to measure cache the effectiveness of the cache
coherency protocol is to monitor the bus used to communicate between
the processors in an SMP system.  This approach provides for some
high level  information, such as, number of retries and in theory, it
can provide information such a...