Browse Prior Art Database

High Speed Byte Parity Generator or Checker in Altera Field Programmable Gate Arrays

IP.com Disclosure Number: IPCOM000118383D
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 6 page(s) / 85K

Publishing Venue

IBM

Related People

Loison, J: AUTHOR

Abstract

ALTERA MAX+PLUS II Compiler (Fig. 1) does not give the optimized solution for a Parity generator or checker in a FLEX 10K Field Programmable Gate Arrays (FPGA). The Compiler uses two Carry chains with two inputs, when it could use three Carry chains with three inputs.

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High Speed Byte Parity Generator or Checker in Altera Field Programmable
Gate Arrays

      ALTERA MAX+PLUS II Compiler (Fig. 1) does not give the
optimized solution for a Parity generator or checker in a FLEX 10K
Field Programmable Gate Arrays (FPGA).  The Compiler uses two Carry
chains with  two inputs, when it could use three Carry chains with
three inputs.

      The VHDL file (listed in Fig. 2) for a Byte Parity generation
is mapped by the MAX+PLUS II Compiler as follows:

                            (Image Omitted)

The eight terms XOR function is performed with two CARRY cells (with
two inputs each) and two normal cells.  The routing is done with two
Carry chains (from a Carry cell to another cell) and one LAB
Interconnect (from a normal cell to another cell).
  Library IEEE;
  Use IEEE.std_logic_1164.all;
  Use IEEE.std_logic_unsigned.all;
  Entity ESSAI is
  Port ( CLOCK           : in    std_logic                ;
         DATA            : in    std_logic_vector(0 to 7 );
         DATA_PAR_GEN    : out   std_logic                );
  End ESSAI;
  Architecture ESSAI_A of ESSAI is
    Signal PAR_GEN         : std_logic;
  Begin
  Process(DATA)
    Variable IS_ODD : std_logic;
  Begin
    IS_ODD := '0';
      For i in 0 to 7 Loop
      IS_ODD := IS_ODD xor DATA(i);
      End Loop;
    PAR_GEN <= not IS_ODD;
  End Process;
  Process(CLOCK)
  Begin
  If (CLOCK'event and CLOCK = '1')
  Then
  DATA_PAR_GEN <= PAR_GEN;
  End if;
  End Process;
  End ESSAI_A;
            Fig. 2  VHDL File for Parity Generator

      The idea is to force the compiler to map in the following
structure by instantiating CARRY primitives.

      As shown in Fig. 3, the eight terms XOR function is now
performed with three CARRY cells (with three inputs each) and one
normal cell.  The routing is done with three Carry chains, improving
the performances.
  Note: For the first Carry cell, the unco...