Browse Prior Art Database

Migratable Library Generation

IP.com Disclosure Number: IPCOM000118407D
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Barth, J: AUTHOR [+2]

Abstract

Disclosed is a method which helps to generate design libraries, including schematics and layouts in a new technology, saving development cost and time at least an order of magnitude. The method described rounds off height and width of layouts and adjusts outputs on wiring grid for compatibility with placement and routing tools. The method helps to remove jogs, stretch, expand shapes, straighten out the bent structures, generate shapes, if necessary, rename the levels/layers necessary for any technology and scale the shapes to achieve high performance for layouts. The method also generates schematics and scales them hierarchically, which match the layouts and the entire library with schematics and layout can be generated automatically.

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Migratable Library Generation

      Disclosed is a method which helps to generate design libraries,
including schematics and layouts in a new technology, saving
development cost and time at least an order of magnitude.  The method
described rounds off height and width of layouts and adjusts outputs
on wiring grid for compatibility with placement and routing tools.
The method helps to remove jogs, stretch, expand shapes, straighten
out the bent structures, generate shapes, if necessary, rename the
levels/layers necessary for any technology and scale the shapes to
achieve high performance for layouts.  The method also generates
schematics and scales them hierarchically, which match the layouts
and the entire library with schematics and layout can be generated
automatically.

      The circuit libraries are an essential part of ASIC or custom
design process.  However, generation of circuit library involving
schematics and layouts for a certain technology is rather an
expensive and time consuming process, e.g., a typical library
consisting of 1200  circuits requires 30-40 man-year effort and
additional 6 months for qualification.  This results into manual
rework of schematics and layout,  which is a laborious and expensive
process.  Also, the qualification of  such libraries is a marathon
task.  To avoid such problems, we have disclosed a method which can
generate libraries and migrate across technologies in a short time.

      The invention relies on the series of algorithms, which migrate
the source library to the desired technology ground rules including
the appropriate shapes and layers.  The invention has following
attributes: the generated library maintains data hierarchy.  It also
minimizes topology change by maintaining accuracy of timing rules.
It provides rapid turn around time by at least an order of magnitude.
It minimizes cost...