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Finite Impulse Response Method of Equalization

IP.com Disclosure Number: IPCOM000118437D
Original Publication Date: 1997-Feb-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 76K

Publishing Venue

IBM

Related People

Hutchins, RA: AUTHOR [+2]

Abstract

Disclosed is a modular Finite Impulse Response (FIR) filter architecture that is fast and efficient in implementation. It uses Booth multipliers to perform the multiplication operation and a pipelined architecture to reduce propagation delays in the logic.

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Finite Impulse Response Method of Equalization

      Disclosed is a modular Finite Impulse Response (FIR) filter
architecture that is fast and efficient in implementation.  It uses
Booth multipliers to perform the multiplication operation and a
pipelined architecture to reduce propagation delays in the logic.

      The basic architecture of the FIR filter implementation is
shown in Fig. 1.  It consists of a set of multipliers and adders
connected serially.  The input XN, is initially latched into a
register and the latched value is multiplied by each of the
programmable coefficients:  H0, H1,...  , Hn.  These product results
can be latched to improve the data rate of the design or used
directly (reduced circuit count).  At each stage of the filter, the
input multiplied by the coefficient (XN times Hn) is added to the
output of the previous stage.  This output is latched into two banks
of registers  that store the carry/sum result of the addition.  This
speeds up the calculations and eliminates the need for a
carry-lookahead adder at each stage (carry-lookahead adders are
relatively slow and hardware intensive).  At the last tap of the
equalizer, the carry/sum result are  summed together using a
carry-lookahead adder (or equivalent) to create  a single result.

      Fig. 2 shows the partitioning of the FIR filter into thirteen
modular blocks or taps (note: the taps can easily be cascaded to
form a FIR of any length).  Each tap receives the latched...